AI Hardware Engineering Intern

Job Details:

Job Description:

About the Job

Intel is seeking exceptional Computer Science, Electrical Engineering, Computer Engineering, and AI/ML students to join an AI Hardware Engineering internship focused on the future of AI inference and AI infrastructure with hardware/software co-design expertise.

This internship approaches AI infrastructure as a hardware/software co-design challenge. The intern will analyze how model architecture, inference behavior, memory movement, data-center constraints, and software stacks influence end-to-end customer outcomes, including throughput, latency, time-to-first-token, tokens per second, power consumption, utilization, total cost of ownership, and deployability.

The successful candidate will be technically hands-on, capable of independent research and analysis, and comfortable working within a highly technical team of researchers and engineers addressing complex AI hardware and infrastructure challenges.

What You Will Do

• Conduct technical research on the next generation of AI infrastructure, including CPUs, GPUs, AI accelerators, ASICs, memory systems, networking, storage, rack-scale architecture, power delivery, cooling, and cluster management.
• Analyze GenAI and agentic AI workloads to understand their hardware implications, including transformer architecture based inference, mixture-of-experts architectures, multimodal models, real-time interactive inference, and distributed serving.
• Evaluate the hardware behavior of AI inference pipelines, including the distinct demands of prompt processing/prefill and token generation/decode, memory capacity, memory bandwidth, KV-cache management, compute utilization, interconnect bandwidth, and latency. For example, cluster architecture around optimizing both prefill and decode through hardware, memory, and system co-design.
• Identify product and system gaps that may limit Intel's ability to serve AI customers effectively, including hardware capabilities, developer tooling, performance libraries, reference architectures, deployment models, observability, and ecosystem enablement.

• Expertise in modern high-performance CPU, GPU, or AI accelerator architecture and hardware/software interactions.

• Support Silicon HW programs through multiple phases of the silicon lifecycle, with end-to-end chip execution from concept to silicon.

• Good understanding with firmware codebases, compilers, kernels, serving stacks and model architectures.

• Familiar with driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon including memory subsystems and interconnects: scale up, scale out, scale across, power management , liquid cooling at rack scale level, deep system level observability & telemetry and dependent impact into Gen AI and LLM level performance/tco/execution KPIs