Custom Memory Design Engineer
Analog design engineer building custom analog/mixed-signal library cells and macros (especially DRAM and other memory circuits) for Normal Computing's unconventional compute-in-silicon architecture. Owns the end-to-end analog flow — clean-sheet circuit design, parasitic extraction, and silicon bring-up — using Cadence tools in Mountain View.
- Compensation
- $200K–$400K / yr
- Location
- Mountain View
- Work setup
- Onsite
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Hardware
- Posted
Skills
Must have
- Developed analog IP from spec to GDSII in modern technologies, taped out and brought up
- Worked on memory technologies (SRAM, DRAM) at core level (bitcell arrays and peripheral circuits)
- Designed and characterized custom bitcells in schematic and layout
- Fluent in the Cadence flow: Virtuoso, Spectre, Assembler, Extraction, Layout, HSMC, Characterization
- Deep understanding of noise and variation and their impacts on silicon performance and reliability
Nice to have
- Lead, taped out, brought up CIM chips
- Comfortable in a chip measurement environment for debug and characterization
- Used AI and/or scripting languages (Python, Perl) to automate design flows and data post-processing
Full description
Normal Computing | Build with Us
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.
The Role
As a Custom Memory Design Engineer, you will build the custom memories that power our unconventional computing architecture.
You will design unique RAM circuits in various RAM technologies, including SRAMs and DRAMs to support a unique computational architecture. Working alongside silicon architecture, digital design, memory architects, and analog design engineers, you will own the end-to-end development of various RAM circuits, from clean-sheet design through closure and tapeout, and silicon bring-up, unlocking unprecedented throughput-per-watt.
What You Will Own
- RAM design flow design and methodology: lead the full custom RAM development cycle, from architecture, establishing methodology, tooling, design, to closure
- Partnership and Acquisition: Develop or acquire RAM IP for use in Normal Silicon, including RAM PDKs
- EDA tooling: Acquire or help direct RAM design EDA tool development
What Makes You a Great Fit
- Developed RAM IP from spec to GDSII in modern technologies, taped out and brought up.
- Worked on memory technologies (i.e. SRAM, DRAM) at the core level (bitcell arrays and peripheral circuits)
- Designed and characterized custom bitcells in schematic and layout
- Fluent in the Cadence flow: Virtuoso, Spectre, Assembler, Extraction, Layout, HSMC, Characterization
- Deep understanding of noise and variation and their impacts on silicon performance and reliability
Bonus Points
- Lead, taped out, brought up CIM chips
- Experienced and comfortable in a chip measurement environment for debug and characterization
- Have used AI and/or scripting languages (i.e. Python, Perl) to automate design flows and data post-processing
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.