Analog Design, Principal Engineer - 15231

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.
• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.
• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.
• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.
• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.
• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.
• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.
• Collaborating with silicon test and debug experts for Sim2Sil correlation.
• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.
• Enhancing the performance and efficiency of high-speed physical interfaces.
• Contributing to the development of cutting-edge technology in High Speed PHY IP.
• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.
• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.
• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .
• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters