Analog IC Layout Designer

Be visionary

Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.​

We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.

Job Description

Join a team developing high-performance analog and mixed-signal ICs for CMOS image sensor applications. You’ll turn transistor-level designs into robust silicon layouts, balancing matching, noise, area, reliability, and manufacturability.

If you enjoy solving layout-dependent performance challenges and collaborating closely with analog designers from schematic through tapeout, this role offers meaningful technical depth within Teledyne Technologies.

What you’ll do

• Create transistor- and block-level layouts for Op-Amps, references, ADC/DACs, PLLs, sensor readout, and high-speed interfaces.
• Optimize floorplans for matching, area, noise isolation, power integrity, and EM reliability.
• Apply common-centroid, interdigitation, symmetry, shielding, guard-ring, and dummy-device techniques.
• Run and resolve DRC, LVS, ERC, density, and fill verification.
• Minimize parasitic coupling, process variation, and layout-dependent effects.
• Support parasitic extraction, post-layout simulation, and tapeout.
• Collaborate with design, process, reliability, verification, and CAD teams.
• Contribute to layout reviews and mentor junior engineers when appropriate.

**What you need

• Required: Strong understanding of analog matching, parasitics, device physics, ESD, and reliability.
• Required: Ability to interpret transistor-level schematics and analog circuit behavior.
• Required: 3+ years of analog/mixed-signal IC layout experience.
• Required: Experience with advanced CMOS technologies and signoff.
• Required: Proficiency with Cadence Virtuoso and Calibre, Assura, or equivalent tools.
• Required: Bachelor’s or Master’s degree in EE, Computer Engineering, Physics, or related field.
• Advantage: CIS, ADC/DAC, PLL, high-voltage, or low-noise sensor-interface experience.
• Advantage: EM/IR, LDE, ESD/latch-up, advanced-node, and tapeout experience.