Analog/Mixed Signal ASIC Design Engineer
- Compensation
- Not disclosed
- Location
- San Diego, California, United States of America
- Work setup
- Onsite
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 2+ years
- Category
- Hardware
- Posted
Skills
Nice to have
- • 2+ years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., VCO, PLL, and DLL design, Audio CODEC and Class D Audio amplifier design, Delta-Sigma, SAR ADC
- Principal Duties and Responsibilities:
- • Uses appropriate tools or databases to contribute to architecture and circuit designs for a small, well-defined block under some guidance. • Works with layout teams to oversee block-level layout. •
- Level of Responsibility: • Working under some supervision. • Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically
- The responsibilities of this role do not include: • Providing supervision/guidance to others. • Influence over key organizational decisions. • Role in strategic planning.
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- Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information
- Pay range and Other Compensation & Benefits:
- The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one compon
- If you would like more information about this role, please contact Qualcomm Careers.
Full description
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Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > Analog Mixed Signal Design
General Summary:
Oversees definition, design, verification, and documentation for development of a variety of CMOS mixed analog/digital blocks such as: data converters, PLLs, analog/digital filters, low drop out linear voltage regulators, precision references, comparators, fingerprint sensor AFE, audio amplifiers and high speed SERDES. Determines architecture design and circuit specifications based on system level requirements. Is actively involved in all aspects of the design from system definition/simulation to circuit design and simulation. Heavy involvement in overseeing layout and silicon evaluation is also expected. Uses design tools such as Cadence ADE, MathWorks MATLAB and others. Provides technical expertise for new initiatives (e.g., 5G, analog design automation).
Minimum Qualifications:
- Bachelor's Degree in Electrical Engineering and 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET.
OR
Master's degree in Electrical Engineering or related field.
- 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).
Preferred Qualifications:
- 2+ years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., VCO, PLL, and DLL design, Audio CODEC and Class D Audio amplifier design, Delta-Sigma, SAR ADCs, Current-Steering DACs, high speed DDR PHYs, high-speed SERDES).
Principal Duties and Responsibilities:
- Uses appropriate tools or databases to contribute to architecture and circuit designs for a small, well-defined block under some guidance.
- Works with layout teams to oversee block-level layout.
- Runs simulations and basic analyses (e.g., power, performance) on designs; documents and shares results with leads, and utilizes feedback to improve and verify designs.
- Programs and runs basic tests to identify bugs in own work; debugs simple issues and escalates complex issues.
- Builds understanding of one's technical domain to ensure integration with other components in the domain.
- Writes technical documentation and design descriptions for straightforward projects under the direction of a supervisor.
- Contributes to conversations to generate new ideas.
Level of Responsibility:
- Working under some supervision.
- Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct).