Skills

Full description

Work in AMS IP Design Verification, in UVM-based verification environment.
Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
Act as Technical Lead of a Design Verification group/team by providing technical guidance, planning schedule and resource to meet requirement for project deliverables, fostering methodology advancement, and so on.
Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.

Quick learner with strong critical thinking and creative problem-solving skills.
Solid knowledge in ASIC design process, digital design and UVM-based design verification methodologies.
Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals,
3+ year Experience as Technical Lead of a Design Verification group/team is preferred.
3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
Power-aware simulations and gate level simulations is a plus
Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
Familiar with programming languages: C, C++, and/or SystemC is a plus.

Analog/Mixed-Signal Design Verification Engineer/Lead

Compensation

Not disclosed

Location

Hefei

Work setup

Not specified

Seniority

Lead

Employment

Not specified

Experience

Not specified

Work in AMS IP Design Verification, in UVM-based verification environment.
Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
Act as Technical Lead of a Design Verification group/team by providing technical guidance, planning schedule and resource to meet requirement for project deliverables, fostering methodology advancement, and so on.
Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.

Quick learner with strong critical thinking and creative problem-solving skills.
Solid knowledge in ASIC design process, digital design and UVM-based design verification methodologies.
Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals,
3+ year Experience as Technical Lead of a Design Verification group/team is preferred.
3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
Power-aware simulations and gate level simulations is a plus
Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
Familiar with programming languages: C, C++, and/or SystemC is a plus.