ASIC Design Senior Staff Engineer
- Compensation
- Not disclosed
- Location
- Shanghai, China
- Work setup
- Onsite
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 4+ years
- Category
- Hardware
- Posted
Skills
Must have
- Deep expertise in ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow
- Deep expertise in Ethernet architecture, including:
- Forwarding pipelines (L2/L3, ACLs, tunneling)
- Traffic management (QoS, scheduling, shaping)
- High-performance packet processing and scaling strategies
- Strong leadership and cross-functional influence capability
- Strong debugging and system-level problem-solving skills
- Excellent teamwork, interpersonal and communication skills.
- Fluent in Chinese and English both verbal and written.
- Ability to work in stressful situations with tight schedules to meet.
- Description of Function & Responsibility
- Drive architecture definition and technical strategy for next-generation Ethernet switch or PON ASICs, enabling scalable, high-performance networking solutions.
- Define architecture and roadmap for Ethernet and packet processing subsystems
- Lead design across multiple subsystems (forwarding engine, traffic management, scheduling, resource allocation)
- Drive cross-functional alignment with HW, SW, and Product teams on networking features and performance targets
- Lead performance analysis, modeling, and trade-off studies for switch architecture
- Mentor senior technical leaders and influence organization-wide engineering direction
- Ensure successful execution from architecture through silicon delivery
- Education:
- MS in EE.
- Experience:
- 8 to 12+ years ASIC design/architecture experience. Experience in merchant silicon or Ethernet or PON is highly desirable.
- Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to provid
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- If you would like more information about this role, please contact Qualcomm Careers.
Full description
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Company:
Qualcomm China
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:Requirements:
Deep expertise in ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow
Deep expertise in Ethernet architecture, including:
Forwarding pipelines (L2/L3, ACLs, tunneling)
Traffic management (QoS, scheduling, shaping)
High-performance packet processing and scaling strategies
Strong leadership and cross-functional influence capability
Strong debugging and system-level problem-solving skills
Excellent teamwork, interpersonal and communication skills.
Fluent in Chinese and English both verbal and written.
Ability to work in stressful situations with tight schedules to meet.
Description of Function & Responsibility
Drive architecture definition and technical strategy for next-generation Ethernet switch or PON ASICs, enabling scalable, high-performance networking solutions.
Define architecture and roadmap for Ethernet and packet processing subsystems
Lead design across multiple subsystems (forwarding engine, traffic management, scheduling, resource allocation)
Drive cross-functional alignment with HW, SW, and Product teams on networking features and performance targets
Lead performance analysis, modeling, and trade-off studies for switch architecture
Mentor senior technical leaders and influence organization-wide engineering direction
Ensure successful execution from architecture through silicon delivery
Education:
MS in EE.
Experience:
8 to 12+ years ASIC design/architecture experience. Experience in merchant silicon or Ethernet or PON is highly desirable.
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.