ASIC Digital Design, Sr Staff Engineer - 18637

Alternate Job Titles

• Digital Design Senior Staff Engineer
• ASIC Design Sr Staff Engineer
• RTL Sr Staff Engineer
• Senior Staff Digital IP Designer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building RTL that actually ships, not just passes simulation. The kind of RTL that holds up under post-silicon scrutiny when customers are integrating your IP into their SoC and every timing path matters. You know that a well-written micro-architecture spec is not documentation for the sake of it, it is the contract between what the protocol demands and what your design delivers.

You are comfortable sitting with a protocol standard document, extracting what matters, and translating it into clean, synthesizable design. When a verification engineer flags a corner case, you do not just patch the RTL, you trace it back to the architecture decision and fix it properly. You have debugged enough SDF-backannotated gate-level simulations to know that the real work starts after RTL freeze.

Working across borders does not faze you. You have collaborated with verification teams in different time zones, supported customer integrations where the stakes are high, and handled post-silicon bring-up calls where every cycle counts. You write code that others can read six months later, and you care about the difference between a design that works in simulation and one that works in silicon.

What You'll Be Doing

• Design and develop high-speed mixed-signal PHY IP blocks in SystemVerilog and Verilog as part of a cross-functional digital design team
• Author detailed micro-architecture specifications based on industry protocol standards, translating requirements into implementable design decisions
• Execute RTL design from concept through tape-out, ensuring design quality through Linting, CDC checks, and adherence to coding standards
• Collaborate with verification engineers to debug and resolve issues in RTL simulations and gate-level simulations with SDF timing annotation
• Provide technical support to customers during SoC integration, post-silicon bring-up, and field deployment
• Participate in design reviews and mentor junior engineers on RTL best practices

The Impact You Will Have

• Your RTL designs will power high-speed connectivity IP used in customer SoCs across automotive, mobile, and data center applications