ASIC Digital Design, Sr Staff Engineer- 19060
- Compensation
- Not disclosed
- Location
- Not listed
- Work setup
- Not specified
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 3+ years
- Category
- Hardware
- Posted
Skills
Must have
- Extensive hands-on experience with 3-10yrs in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
- Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.
- Strong understanding of digital logic design, RTL coding, and verification principles.
- Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.
- Solid scripting skills (e.g., TCL, Perl, Python) to automate design and test flows.
- Collaborative team player who communicates effectively across functions and cultures.
- Proactive problem solver, comfortable with ambiguity and rapid change.
- Detail-oriented and highly organized, with a commitment to delivering high-quality results.
- Inclusive and open-minded, eager to share knowledge and mentor others.
- Self-motivated and driven by curiosity, with a continuous learning mindset.
Full description
**Job Description and RequirementsWe Are:
**At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.
** What You'll Be Doing:
- Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.
- Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
- Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
- Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
- Collaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows.
- Contribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time.
**The Impact You Will Have:
- Enhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.
- Drive innovation in DFT flows, setting new standards for quality and efficiency within the organization.
- Enable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.
- Represent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.