ASIC Digital Design, Staff Engineer - 19291
- Compensation
- Not disclosed
- Location
- Not listed
- Work setup
- Not specified
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 3+ years
- Category
- Hardware
- Posted
Skills
Must have
- Bachelor’s or master’s degree in Computer Engineering, Electrical Engineering, or Communication Engineering.
- 5+ years of ASIC design verification, UVM-based functional verification, or related experience (3+ years with a master’s degree).
- Solid SystemVerilog and UVM skills, including testbench architecture, agents, and test sequences.
- Hands-on experience working within AI-assisted development flows, using coding agents such as Cursor, Claude Code, or GitHub Copilot.
- Proficiency in scripting languages (Python, Tcl, Perl, Unix shell).
- Strong analytical skills and the ability to work in a dynamic, fast-paced team environment.
Full description
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You are an ASIC verification engineer who cares as much about how verification gets done as about what gets verified. You have solid hands-on UVM experience, and when you see a repetitive or fragile step in the flow, your first instinct is to automate it. AI coding agents are already part of how you work every day: you use them to write, review, and maintain code, and you know where they help and where they need a careful human eye.
At Synopsys, you will join the R&D team developing the PCI Express (PCIe) and Compute Express Link (CXL) controller IP used in data centers, artificial intelligence, automotive, and many other applications. The verification components and flows you build will be used by the whole team, every day.
- Verification engineer at heart, automation engineer by instinct: you bridge UVM testbenches and the scripts and infrastructure around them.
- AI-native: you work comfortably within AI-assisted flows and use coding agents such as Cursor, Claude Code, or GitHub Copilot as everyday tools.
- Owner: you take a component or a flow from requirements to deployment and support, with general direction rather than step-by-step instructions.
- Multiplier: the tools and components you build make the engineers around you faster.
What You’ll Be Doing
- Design, deploy, maintain, and support reusable and configurable verification components for PCIe and CXL controller IP.
- Develop UVM testbench architecture, agents, and test sequences within your area of the verification environment.
- Build and extend AI-assisted flows for verification and automation, using coding agents such as Cursor, Claude Code, or GitHub Copilot to create, review, and maintain testbench code, scripts, and regression infrastructure.
- Integrate state-of-the-art Synopsys tools into the product workflow.
- Work with the infrastructure team to ensure fair and efficient access to shared compute and tool resources.
- Contribute to internal forums on verification methodology, automation, and AI-assisted development best practices.
- Coach more junior engineers on UVM, automation, and effective use of AI coding agents.
The Impact You Will Have
- Shorten verification turnaround for PCIe and CXL IP by automating repetitive and error-prone work across the flow.