ASIC Implementation Specialist

ASIC Implementation Specialist

Location: Amsterdam, Netherlands

Department: Development (Group)

As an ASIC Implementation Specialist in our Global Hardware R&D team, you’ll help expand IMC’s ASIC capabilities, building on our existing technology to accelerate time-to-market.

You’ll work on greenfield projects spanning cutting-edge research and production-scale implementations, with multiple overlapping projects each year. This is an opportunity to help shape the future of ASICs at IMC and contribute to technology that will support our trading systems over the next decade.

Your Core Responsibilities:

• Take ownership of blocks throughout the RTL-to-GDSII back-end flow: synthesis, floorplanning, clock-tree synthesis, timing optimization and signoff.

• Design floorplans and power grids, making key decisions around macro and pin placement, area budgeting and clock-tree optimization.

• Drive STA and timing closure for high-performance designs, developing and validating the SDC constraints needed to achieve design goals.

• Ensure designs are ready for signoff through power integrity analysis, physical verification, logic equivalence checking and ECOs.

• Shape and improve implementation flows around design needs, building automation and scripts that support efficient execution.

• Work closely with RTL design, DFT, packaging and foundry teams, using physical implementation insights to influence and improve RTL.

• Share your expertise through design reviews and clear documentation.

Your Skills and Experience:

Required Experience:

• BS/MS in Electrical or Computer Engineering, with 7+ years of ASIC implementation experience and multiple successful tapeouts.

• Strong experience across physical implementation and signoff, including floorplanning, clock-tree synthesis, STA, timing closure and physical verification.

• Hands-on experience with Cadence and Siemens implementation and signoff tools.

• Strong understanding of CMOS, RC-parasitic extraction and key physical design formats and constraints.

• Experience with low-power design flow.

• DFT awareness.

• Advanced FinFET nodes experience (16/12/7/5).

Preferred Experience:

• Experience with custom macro integration.

• Knowledge of package/PCB co-design, chiplet or 2.5D/3D integration.

• Exposure to machine-learning-driven implementation flows.