ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)
- Compensation
- Not disclosed
- Location
- Bangalore, India
- Work setup
- Onsite
- Seniority
- Lead
- Employment
- Not specified
- Experience
- 1+ years
- Category
- Hardware
- Posted
Skills
Must have
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Nice to have
- 3 to 8 years of strong experience in RTL design for ASICs
- Expertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains
- Familiar with UPF and power domain crossing
- Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP
- Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
- Experience in low power design methodology and clock domain crossing designs
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in formal verification with Cadence LEC
- Understanding of full RTL to GDS flow to interact with DFT and PD teams
- Expertise in Perl/TCL/Python language
Full description
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Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:Job Description
This role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.
Key Responsibilities
- Micro-architecture and RTL design for IP Cores / subsystems.
- Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.
- Enable SW teams to use HW blocks.
- Qualify designs using static tool checks including Lint, CDC, CLP etc.
- Synthesis, LEC and Netlist CLP
- Report status and communicate progress against expectations.
Preferred Qualifications
- 3 to 8 years of strong experience in RTL design for ASICs
- Expertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains
- Familiar with UPF and power domain crossing
- Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP
- Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
- Experience in low power design methodology and clock domain crossing designs
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in formal verification with Cadence LEC
- Understanding of full RTL to GDS flow to interact with DFT and PD teams
- Expertise in Perl/TCL/Python language
- Experienced in database management flows with Clearcase/Clearquest.
- Expertise in post-Si debug is a plus
- Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members.
- Team player, self-motivated, should be able to work with minimal supervision.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).