CPU Server Physical Design Clock Engineer
- Compensation
- Not disclosed
- Location
- Austin, Texas, United States of America
- Work setup
- Onsite
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 2+ years
- Category
- Design
- Posted
Skills
Must have
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- Pay range and Other Compensation & Benefits:
- The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one compon
- If you would like more information about this role, please contact Qualcomm Careers.
Nice to have
- MS in Electrical Engineering; 8+ years of practical experience.
- Skilled in chip physical design, standard cell optimizations, and clock construction.
- Defined clock methodology across various designs.
- Preferred experience in deep submicron process technology nodes.
- Proficient in PLL specifications, clock skew estimation, and jitter measurements.
- Strong communication skills for team collaboration and issue resolution.
Full description
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Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > CPU Engineering
General Summary:
As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to create best in class clocking solutions for next generation CPUs.
Minimum Skillsets
- Experience in all aspects of construction and analysis of low skew and low power clock generation and distribution.
- Experience in clock H-tree, mesh, spines and CTS implementations.
- Good understanding of device physics, RC delay and electrical aspects.
- Proficiency in SPICE simulation and analysis for circuit design and verification.
Preferred qualifications
- MS in Electrical Engineering; 8+ years of practical experience.
- Skilled in chip physical design, standard cell optimizations, and clock construction.
- Defined clock methodology across various designs.
- Preferred experience in deep submicron process technology nodes.
- Proficient in PLL specifications, clock skew estimation, and jitter measurements.
- Strong communication skills for team collaboration and issue resolution.
Roles and Responsibilities
- Work with design teams to understand, implement and validate CPU clocking.
- Drive overall clock generation and distribution methodology of CPU.
- Work with CAD & block level designers to implement the clocking techniques for optimizing skew and power.
- Perform jitter analysis and measurements and provide feedback to block level and top level physical design engineers on key fixes required.
This position is open to both locations Austin and Santa Clara. The compensations will be adjusted based on the location.
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.