<Data center>Digital IC Integration Technical Manager_Hsinchu/Taipei

• SoC chip integration from RTL to gate level including timing closure and testability
• Whole chip DFT structure planning and design
• Whole chip timing review and closure sign-off
• Design methodology and integration flow improvement
• Chip TOP IO and floorplan planning and TOP glue circuit design
• Work location: Hsinchu/Taipei

Requirements

• Chip level integration experience
• Familiar with frontend or backend implementaion flow and related EDA tools

including: DFT/BSD/TestKompress, Tempus/PrimeTime/PrimeClosure

• Experience about DFT Integraiton or STA timing sign-off
• Solid knowledge of clock, timing constrain, CTS and physical implementation

Education: Master's Degree