<Data center>Senior Digital Design and IP Integration Engineer

• Own the top-level integration of internal and third-party IPs into SOC or FPGA platform.
• Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan.
• Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience of hands-on experience in ASIC/SOC design with strong proficiency in RTL design.
• Experience with EDA tools for synthesis, lint, CDC, simulation, and debug.
• Experience with high speed interface and DRAM controller are preferred.