MediaTek
<Data center>Senior SerDes Design Verification Engineer
- Compensation
- Not disclosed
- Location
- HsinChu
- Work setup
- Not specified
- Seniority
- Senior
- Employment
- Not specified
- Experience
- Not specified
- Category
- Design
- Posted
Skills
Full description
- SerDes design verification in I/O Chiplet to collaborate with analog/digital/algorithm design teams and system application team from prototype test chip to mass production.
- Responsible for implementing test script or designing test firmware for SerDes Analog IP quailification and PHY performance validation
- Responsible for establishing automatic test program and data analysis for SerDes Analog IP and PHY characterization and failure analysis.
- Master's degree in electrical engineering, communication, or equivalent
- Knowledgeable about Wireline Communication principle, such as SerDes, Ethernet, PCIe, USB, MIPI, and etc.
- Experience with test script development or test firmware design
- Knowledgeable about analog or digital Frontend principle, such as Rx, Tx, PLL, CDR, EQ, and etc is plus
- Experience with automated test development is a plus
- Experience with test instruments (PPG, BERT, Scope, etc) operation is a plus
- Familiar with Python, Visual Studio and MATLAB is a plus.