Design Verification Emulation, Hardware
River AI is hiring an emulation-focused design verification engineer to verify IP and SoC hardware for its personal AI devices on emulation platforms like Palladium, Protium, ZeBu, and HAPS. Day to day the role translates DV plans into emulation workloads, builds models and infrastructure, debugs failures with DV block owners, and provides emulation signoff, using Python/SystemVerilog and agentic
- Compensation
- $200K–$420K / yr
- Location
- Austin, TX, Palo Alto, CA
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 5+ years
- Category
- Hardware
- Posted
Skills
Must have
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of industry experience
- Hands-on experience with platforms such as Cadence Palladium/Protium, Synopsys ZeBu/HAPS, or comparable systems, including bring-up, model integration, compilation, execution, and debug
- Experience building or adapting models and test environments for simulation acceleration, emulator-hosted verification, or both
- Strong understanding of verification planning, regression strategy, and verification closure
- Experience verifying complex IP or SoCs, from block-level to system-level testing
- Proficiency in SystemVerilog, C/C++, and scripting languages such as Python, Tcl, or Bash
- Ability to assess which tests and workloads are effective on emulation platforms, balancing runtime, fidelity, observability, and debug
- Collaborative mindset and bias for action working across design, verification, software, and infrastructure teams
Nice to have
- Experience using emulation for long-running software workloads, firmware and driver validation, system-level scenarios, or pre-silicon software bring-up
- Background developing synthesizable test components, transactors, behavioral models, or emulation-friendly replacements for simulation models
- Experience with UVM-based verification environments and adapting them for acceleration or emulation
- Familiarity with coverage-driven verification and SystemVerilog Assertions (SVA)
- Experience using emulation workloads for performance verification and power estimation
- Experience with high-performance silicon such as CPUs, GPUs, AI accelerators, or complex SoCs
- Experience with workflow management, CI/CD, regression definition and visibility, and EDA tool configuration and usage
Full description
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
Who we are
We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
About the Role
We are seeking an emulation-focused design verification engineer to drive IP and SoC verification on emulation platforms. Working with simulation-based DV teams, you will translate architectural and microarchitectural definitions into workloads suited to emulation, then adapt and run those tests. You will partner with DV block owners on debug and emulation-specific closure, providing emulation signoff as an input to overall verification signoff. You will also develop the models and infrastructure needed to support this work.
What You’ll Do
- Verification Strategy & Planning: Translate IP and SoC verification plans into execution strategies, mapping tests to simulation, simulation acceleration, or emulator-hosted verification based on runtime, fidelity, and debug needs. Define emulation workload goals and run acceptance criteria with DV block ownersEmulation Models: Build and maintain models and test components for simulation acceleration and emulator-hosted verification flows, balancing fidelity, performance, and debug visibility.
- Emulation Infrastructure: Develop and improve platform bring-up, compile, mapping, runtime, regression, and debug flows.
Testbench and Workload Development: Adapt or develop test environments, transactors, stimulus, and software-driven workloads that run effectively on emulation platforms.
- Emulation Closure and Signoff: Track workload execution and failures, review results with DV block owners, and help close emulation-specific gaps. Provide emulation signoff as an input to overall IP and SoC verification signoff.
- Emulation Debug and Collaboration: Triage emulation compile, runtime, and test failures; use traces, waveforms, and platform diagnostics to isolate design, model, testbench, or infrastructure issues; partner with RTL and DV block owners to resolve them.
- Agentic AI for Emulation: Build and apply agentic workflows across workload planning, model and test preparation, platform setup, run orchestration, failure triage, result analysis, and closure reporting, improving engineering throughput while keeping results traceable and reviewable by DV owners.