Design Verification Engineer

About Group:

Part of the ATD – Advanced Technology Group group of TI. We are a Team working on High-Density Flash Memory. The flash memory is used in various Connectivity, Industrial, Automotive and Application specific control applications. You will be a part of Flash Controller IP Design Verification Team, working on verification of the flash memory controller.

What will you be doing in this role? (Responsibilities)

• Own part of IP DV from verification strategy to sign-off

• Coverage strategy & coverage closure (Functional, Code & Assertion coverage)

• Develop Test plans, verification strategy, test cases

• Use the right Verification strategy: Simulation, Formal, etc.

• Develop UVM components like agents, drivers, monitors and scoreboards

• Write assertion checks for DUT

• Use Formal apps like Connectivity, COV, UNR, FPV, etc.

• Debug the failures & report RTL bugs/Fix testbench

• Own the regressions for IP

• Improve the existing flows using latest methodologies/technologies

• Bachelors/Masters in VLSI or related field

• 5-10 yrs. Of Digital Design Verification

• Strong command in System Verilog & UVM

• Creating DV environment or tests for IP-level digital DV/SoC level

• Developing DV testbenches, tests, assertion checking for DUT

• Experience in Verification tools like: Xcelium, JasperGold or similar

• Experience in Function & Code analysis & Closure

• Excellent debugging skills

• RTL Coding experience is a plus

• Experience in embedded memory verification is a plus

• Mixed digital/analog simulation (Verilog, AMS) is a plus

• Formal Verification experience is a plus

• Should be able to work with US Team

What do we expect from you? (Mini Qualifications)

• Bachelors/Masters in VLSI or related field

• 5-10 yrs. Of Digital Design Verification

• Strong command in System Verilog & UVM

• Creating DV environment or tests for IP-level digital DV/SoC level

• Developing DV testbenches, tests, assertion checking for DUT

• Experience in Verification tools like: Xcelium, JasperGold or similar

• Experience in Function & Code analysis & Closure

• Excellent debugging skills

• RTL Coding experience is a plus

• Experience in embedded memory verification is a plus

• Mixed digital/analog simulation (Verilog, AMS) is a plus

• Formal Verification experience is a plus

• Should be able to work with US Team