DFT Engineer

CDI à 100% de suite ou à convenir.Postulation uniquement en ligne - merci de mentionner sous source (ORP)Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.Key Responsibilities:Hierarchical MBIST and scan insertion, BSD implementationATPG pattern generation, coverage analysis, converging to high coverage metricsPattern simulations with timingDefining test mode timing constraints, analyzing the timing reports and converge timingDeveloping cycle accurate functional patterns using IJTAG methodologyClosely working with the test and production engineering teams to debug and bring up devices at probe and final testDebugging silicon issuesSkills:Excellent communication skills, and strong team player with can do type of attitudeExcellent debugging skillsGood scripting skills to develop automationQualifications:5+ years of DFT experience including implementation, test pattern development, and simulationProven experience in contributing to DFT solution to complex designsExperience working with IJTAG methodologiesExperience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologiesExperience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metricsGood debug capabilities in simulating patterns with timingExperience with industry standard EDA tools for DFT, timing, and simulationKnowledge of System VerilogEducation:Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)