DSP / NPU Design Verification Sr Staff Engineer

Skills

• ai
• asic
• assembly
• automation
• bash
• fpga
• oop
• perl
• python
• rest-assured
• rtl
• systemverilog
• uvm
• verilog

Must have

1. Job Summary:
2. · Position for 12+ years of experience in design verification of complex Qualcomm propriety DSP/NPU IP
3. · DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.
4. · Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.
5. Job Responsibilities:
6. · Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.
7. · Implement and improve System Verilog/UVM Testbench Architecture.
8. · Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.
9. · Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.
10. · Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.
11. · Complete all required verification activities at IP level and ensure high quality commercial success of our products.
12. · Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a d
13. · Responsible gate level simulation bring-up, gate level verification with timing simulations.
14. · Responsible for power aware RTL verification and gate level simulation.
15. Skillset/Experience:
16. · 12+ years experience in processor/ASIC design verification
17. · Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.
18. · Expertise in System Verilog Testbench Architecture and implementation.
19. · Experience in writing C based and assembly level testcases is preferred.
20. · Exposure to power aware implementation and verification using UPF is a plus.
21. · Experience with advanced verification techniques such as formal and assertions is a plus.
22. · Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware.
23. · Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .
24. · Scripting/Automation Skills — Perl, Python, Shell, Make file TCI .
25. · Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.
26. · Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.
27. · Experience in verification of Processor subsystems is preferred.
28. · Experience in creating validation suite and building automation.
29. · Should have excellent inter-personal and communication skills.
30. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committ

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