Embedded SW/Firmware Design Engineer
Designs and implements complex FPGA/RTL designs (Verilog/SystemVerilog, Vivado, Zynq/Ultrascale+/Versal) for CHAOS Industries' next-generation radar sensor products, covering the full FPGA lifecycle through timing analysis, hardware integration, and support of deployed systems. Full-time on-site in Hawthorne, CA.
- Compensation
- $160K–$290K / yr
- Location
- Hawthorne, California, United States
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Full time
- Experience
- 5+ years
- Category
- Embedded
- Posted
Skills
Must have
- Bachelor's or higher in Computer Engineering, Electrical Engineering, Computer Science or related field
- 5+ years professional digital RTL design targeting FPGAs
- Full FPGA design lifecycle: RTL design, behavioral simulation, place and route, timing analysis, hardware integration
- Extensive experience with Verilog and SystemVerilog
- Extensive experience with ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream)
- Extensive experience with AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale/Ultrascale+, Versal)
- Experience with network protocols (TCP/UDP/IP)
- Experience with serial protocols (I2C, JTAG, UART, SPI, CAN)
- Experience using Bash and Python for scripting and testing
- Experience modifying software drivers and applications to validate FPGA designs
- Experience with Agile processes (Scrum, Continuous Integration, Test-Driven Development)
- Ability to work with minimal supervision and collaborate on small teams
- U.S. Person status required (access to U.S.-only data systems)
Nice to have
- Highly performant baseband signal processing in FPGA
- Translating high-level algorithms from Simulink/MATLAB into RTL incl. FPGA Vendor IP
- Developing software drivers (C/C++/Python) to interface with FPGA designs
- FPGA Ethernet IP blocks (1G/10G/40G/100G)
- Software-Defined Radios (SDRs) e.g. Ettus, NI, HackRF
- Analog Devices transceivers
- Ground or airborne sensors (radars, EO/IR, EW)
- Time synchronization technologies (NTP/PTP)
- HLS synthesis and languages (C/C++/SystemC/Chisel)
- VHDL
- High-speed, multi-layer digital PCB design
- Current or previous DoD security clearance
- Experience with GPUs and/or AI engines
- Experience with git
- Bitbucket CI, Jenkins or similar CI/CD flows
- DoD System/SW architectures and messaging standards (OMS, SOSA, Link-16)
Full description
CHAOS Industries is redefining modern defense with omniscient systems purpose-built for today’s realities. Designed and built by top U.S. military veterans and Silicon Valley innovators, CHAOS Industries’ products are powered by Coherent Distributed Networks (CDN™), empowering warfighters, commercial air operators, and border protection teams to act faster, adapt rapidly, and stay ahead of evolving threats. In a world where technological threats move at unprecedented speed, CHAOS Industries delivers advanced sensing and detection solutions that give the ultimate advantage: time.
CHAOS Industries was founded in 2022 and has raised $1B in total funding from leading investors including 8VC, Accel, and NEA. The company is headquartered in Los Angeles, with offices in Washington, D.C., San Francisco, Seattle, and London. For more information, please visit .
Role Overview:
CHAOS is seeking a highly-skilled and motivated FPGA Engineer to join our team supporting our R&D and product engineering initially focusing on our next-generation radar products. This is a highly collaborative role which will allow you to work on multiple capabilities within our product offerings. As a member of our engineering team, you also have the opportunity to expand your skillset across our product families.
Responsibilities:
- Design and implement complex FPGA designs targeting our next-generation sensor products
- Support system integration of FPGA designs with complex software systems
- Support deployed FPGA capabilities in the hands of our U.S. and international customers
- Work full-time on-site in our office in Hawthorne, California
Minimum Requirements:
- Bachelor’s or higher degree in Computer Engineering, Electrical Engineering, Computer Science or related degree
- 5+ years of experience in a professional setting performing detailed digital RTL design targeting FPGAs
- Extensive experience with the entire FPGA design life cycle: RTL design, behavioral simulation, place and route, timing analysis, hardware integration
- Extensive experience developing in Verilog and SystemVerilog
- Extensive experience with the ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream)
- Extensive experience with the AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale/Ultrascale+, Versal)
- Experience with Network Protocols (TCP/UDP/IP)
- Experience with Serial Protocols (I2C, JTAG, UART, SPI, CAN)
- Experience using Bash and Python for scripting and testing
- Experience modifying software drivers and applications when needed to validate FPGA designs