Expert IC Package Design Lead
Leads the design and development of advanced semiconductor package architectures for high-performance AI connectivity chips, collaborating with cross-functional teams to optimize electrical, thermal, and mechanical performance from concept to production.
- Compensation
- Not disclosed
- Location
- Israel
- Work setup
- Not specified
- Seniority
- Lead
- Employment
- Not specified
- Experience
- 10+ years
- Category
- Design
- Posted
Skills
Must have
- 10+ years of hands-on IC BIG package design experience for high-performance semiconductor products, with full ownership from concept through tape-out
- Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP)
- Strong package architecture & integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
- Deep understanding of signal, power, and thermal integrity at the package level, with ability to drive design tradeoffs based on analysis
- Proven manufacturing and release experience, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs
Nice to have
- Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
- Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
- Experience supporting chiplet-based architectures and heterogeneous integration
- Prior technical leadership or package ownership on high-volume products
Full description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .
Role Overview
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling Astera Labs’ products to operate reliably in the world’s most demanding AI and cloud environments.
Key Responsibilities
- Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
- Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
- Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
- Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
- Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
- Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets