Expert Logic Design Engineer
- Compensation
- Not disclosed
- Location
- Poland
- Work setup
- Remote
- Seniority
- Not specified
- Employment
- Full time
- Experience
- 6+ years
- Category
- Engineering design
- Posted
Skills
Must have
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience
- 6+ years of professional experience in complex FPGA or ASIC digital logic design
- Expert-level proficiency in SystemVerilog RTL design (mandatory)
- Extensive experience defining digital architectures and microarchitectures for complex hardware systems
- Proven track record of independently delivering complex digital IP or subsystems from specification to implementation
- Deep understanding of RTL optimization, logic synthesis, static timing analysis (STA), and timing closure
- Strong experience optimizing digital designs for deterministic latency, high clock frequencies, resource utilization, and power efficiency
- Advanced knowledge of synchronous digital design, CDC, clocking architectures, and hardware interfaces
- Strong understanding of FPGA and/or ASIC development methodologies and implementation constraints
- Experience with simulation-based verification and debugging of complex digital systems
- Ability to evaluate architectural trade-offs, resolve challenging technical issues, and guide implementation decisions
- Strong technical leadership, analytical, and communication skills
- English proficiency sufficient for effective collaboration within an international engineering team
Nice to have
- Extensive experience with AMD/Xilinx FPGA architectures, particularly AMD Versal
- Advanced experience with AMD Vivado, FPGA implementation, and timing closure
- Familiarity with Synopsys VCS, Siemens Questa, and related verification/debugging tools
- Experience with ASIC digital IP development and FPGA-to-ASIC design considerations
- Experience designing complex DSP pipelines, waveform generation engines, or real-time control architectures
- Deep understanding of deterministic, nanosecond-scale timing and synchronization
- Experience with high-speed interfaces such as AXI, PCIe, DDR, or proprietary interconnects
- Experience with performance, area, and power (PPA) optimization
- Knowledge of Python, Tcl, or other languages used for EDA workflow automation
- Experience leading technical design reviews or mentoring senior engineers
- Background in quantum computing, semiconductor development, telecommunications, high-performance instrumentation, or similar advanced technology domains
Full description
Ciklum is looking for an Expert Logic Design Engineer to join our team full-time in Poland.
We are a custom product engineering company that supports both multinational organizations and scaling startups to solve their most complex business challenges. With a global team of over 4,000 highly skilled developers, consultants, analysts and product owners, we engineer technology that redefines industries and shapes the way people live.
About the role:
We are looking for an Expert Logic Design Engineer to take a leading technical role in the architecture, design, and optimization of next-generation FPGA and ASIC-based control platforms.
This position involves solving challenging digital design problems with extremely demanding timing, latency, and performance requirements. You will work closely with system architects, verification engineers, software developers, and hardware specialists, driving technical decisions and contributing to the development of proprietary digital IP.
Our client is an innovative technology company developing advanced control and measurement systems for quantum computing. Its hardware and software platforms enable precise, real-time control of complex quantum systems, supporting the evolution of quantum computing from individual qubits to large-scale architectures.
Responsibilities:
- Lead the architecture, microarchitecture, and RTL implementation of complex, high-performance FPGA/ASIC digital subsystems
- Design and optimize highly configurable, ultra-low-latency digital logic using SystemVerilog
- Drive end-to-end digital IP development, from system requirements and architectural trade-offs to RTL implementation and integration
- Make architectural decisions to optimize timing performance, latency, resource utilization, scalability, and power efficiency
- Address complex timing closure, clock-domain crossing, synchronization, and critical-path optimization challenges
- Develop advanced digital processing and control architectures, including signal processing pipelines, waveform generation, and deterministic real-time control
- Define hardware-software interfaces and collaborate with software and system architecture teams to ensure efficient system integration
- Work closely with verification engineers to define verification strategies and ensure robust functional coverage
- Review RTL designs, identify architectural and implementation risks, and provide technical guidance to other engineers
- Contribute to the evolution of FPGA-based platforms and the development of reusable digital IP for future ASIC implementations
- Drive engineering best practices, design quality, and technical improvements across the development lifecycle