FPGA Design Engineer

We are building the next generation of distributed, ultra-low latency control stacks for massive-scale compute architectures. Our technology powers world-class research facilities and industrial systems globally, pushing the absolute limits of synchronization, high-frequency analog interfacing, and real-time data processing.

Imagine orchestrating thousands of parallel, interconnected nodes with nanosecond-level deterministic synchronization and all-to-all connectivity. If you want to solve the ultimate design and verification scaling challenges at the physical-to-digital frontier, this is where you belong.

You will collaborate daily with electrical engineers, embedded software teams, and domain scientists. We value extreme ownership; you’ll have a direct hand in shaping architecture, influencing high-level technical decisions, and constantly injecting new methodologies from the ASIC/FPGA industry into our stack.

Your Role:

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Architect & Implement: Translate complex, high-throughput requirements into robust VHDL designs.

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Verify at Scale: Author self-checking testbenches at the module level and contribute to scaling our top-level UVM verification environments.

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Integrate & Optimize: Dig into internal and third-party vendor documentation (advanced FPGAs, high-speed ASICs) to optimize hardware-software boundaries.

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Collaborate & Mentor: Act as a technical sparring partner to a diverse digital design and embedded team, proactively pitching architectural improvements.

What You Bring:

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4+ years of experience shipping complex designs in a fast-paced, cutting-edge R&D environment.

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Deep mastery of VHDL and the Xilinx Vivado or Intel Quartus toolchains.

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Hands-on experience with high-end simulation platforms (e.g., QuestaSim).

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Strong grasp of processor and bus-system architectures (e.g., AMBA AXI, Avalon).

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Fluent with Git and scripting for automation (Python, Tcl, Shell).

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Hands-on experience with Xilinx Zynq / UltraScale+ / RFSoC architectures.

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Familiarity with (System)Verilog and advanced verification frameworks (UVM, OSVVM, Cocotb).

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A track record of conquering complex timing closure issues.

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Background in DSP, microarchitecture design, or C/C++ / Linux kernel development.

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Exposure to cryogenic, RF, or advanced physics control instrumentation.