Qualcomm
FPGA Emulation Engineer, up to Staff
- Compensation
- Not disclosed
- Location
- Hsinchu City, Taiwan
- Work setup
- Onsite
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 2+ years
- Category
- Hardware
- Posted
Skills
Must have
- Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 3+ years of hands-on experience in SoC FPGA integration
- Proficiency in SoC emulation methodologies
- Strong understanding of chip-level communication protocols and subsystem interaction
- Strong scripting skills in Python, Tcl, or Shell and AI prompt skills
- Excellent problem-solving and cross-functional communication skills
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Nice to have
- Extensive experience in SoC FPGA emulation and multi-FPGA system integration.
- Strong hands-on experience with Synopsys HAPS or comparable FPGA-based emulation platforms.
- Solid understanding of FPGA architecture, synthesis, placement, routing, timing analysis, and timing closure.
- Experience with standard SoC interfaces, including AXI, AHB, and APB.
- Familiarity with high-speed I/O technologies such as DDR, MIPI, USB, and PCIe.
- Experience debugging issues across simulation, emulation, and software-validation environments.
- Strong system-level debugging, communication, and cross-functional collaboration skills
- Comfortable working in a globally distributed engineering environment
Full description
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Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.
We are seeking an experienced SoC FPGA Emulation Engineer to join our SoC Design team. In this role, you will be responsible for developing and integrating large-scale SoC emulation platforms using Synopsys HAPS systems or other 3rd party solutions. You will also help ensure efficient emulation execution across complex SoC subsystems while driving FPGA integration, implementation quality, verification coverage, timing closure, and cross-functional collaboration.
Responsibilities
- Build and integrate large scale SoC emulation platforms using multiple Synopsys HAPS systems.
- Optimize communication and data flow between internal subsystems (e.g., CPU, memory, interconnect, peripherals) on FPGA-mode.
- Develop and integrate FPGA-mode interfaces, such as AXI, AHB, APB and others and optimize subsystem connectivity across multiple HAPS machines.
- Develop and manage FPGA-mode clock and reset architecture across multiple HAPS systems.
- Collaborate with High-Speed IO designers, including DDR, MIPI, USB and PCIe, etc., to integrate related FPGA high-speed IO models and daughter boards to enable comprehensive emulation coverage.
- Apply in-depth knowledge of FPGA architecture, synthesis and implementation to Maximize FPGA utilization, achieve timing closure and deliver bitfiles on time.
- Debug and resolve integration issues across simulation, emulation, and software-validation environments.
- Support system-level bring-up, performance analysis, and correlation activities during emulation.
- Work closely with design, verification, software, and platform teams to identify risks, improve emulation efficiency, and ensure project milestones are met.
Minimum Qualifications
- Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 3+ years of hands-on experience in SoC FPGA integration
- Proficiency in SoC emulation methodologies
- Strong understanding of chip-level communication protocols and subsystem interaction
- Strong scripting skills in Python, Tcl, or Shell and AI prompt skills