FPGA Engineer

Responsibilities

• Algorithm implementation: Translate complex probabilistic algorithms from high-level models, such as pseudocode/Python/C++/MATLAB, into highly pipelined, resource-efficient FPGA RTL.

• RTL design from scratch: Design and implement custom digital logic using VHDL where off-the-shelf vendor IPs are insufficient, bottlenecked, or introduce latency.

• High-speed I/O integration: architect data acquisition pipelines interfacing with the analogue front end via ultra-fast ADCs and high-speed transceivers, as well as interfacing to high-throughput computer host architectures via PCIe and high-speed Ethernet.

• System architecture: Work closely with hardware and software engineers, the research team, and ASIC architects to develop the high-level system architecture.

• Verification & bring-up: Develop rigorous testbenches and simulations to ensure compliance with functional and timing requirements. Participate in lab bring-up and debugging of physical hardware.

• Optimisation: Use advanced debugging tools and techniques to analyse and optimise performance, timing closure, power consumption, and resource utilisation across multiple clock domains.

Requirements

• Degree in Electrical Engineering, Computer Engineering, or a related field.

• 5+ years of hands-on experience in FPGA digital design, including designing and debugging resource-intensive high-speed digital systems.

• Expertise in HDL: Strong proficiency in HDL coding, and a proven track record of writing custom RTL from scratch.

• PS/Embedded development knowledge: Practical understanding of processor-side development for FPGA SoC platforms, particularly Zynq or similar PS/PL architectures. Being comfortable writing or reviewing bare-metal C/C++ to configure PL peripherals through AXI registers, moving data between PS and PL.

• Math to hardware: Proven ability to translate complex mathematical models into hardware accelerators, including bit-accurate system modelling and fixed-point arithmetic.

• Digital design fundamentals: Solid understanding of advanced digital design concepts, including timing closure for highly utilised designs and clock domain crossing (CDC).

• Toolchains: Deep experience with design and verification tools such as Xilinx Vivado, Vitis, and TCL scripting.

• Lab/debug skills: Familiarity with hardware debugging tools, such as JTAG debuggers, oscilloscopes, spectrum analysers, signal generators, and logic analysers, and lab bring-up of custom boards.

What makes you stand out

• Synchronised FPGA interconnect network within a scalable cluster approach.