FPGA Silicon Design Verification Engineer
- Compensation
- Not disclosed
- Location
- Bengaluru, Karnataka, India
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 5+ years
- Category
- Hardware
- Posted
Skills
Must have
- MSEE/BSEE or equivalent with 5 years of experience in IP / SoC design verification.
- Strong in System Verilog, UVM, Verilog
- Strong in coverage-based verification methodology with assertions
- Knowledge on PCIe is a must
- Familiar with Perl, Python, Java is a plus
- Familiarity with Intel Quartus or Xilinx Vivado is a plus.
- Strong skills in communication, initiative, promote innovation and teamwork
- Highly motivated to learn and adapt to fast changing technologies and environments
- Demonstrates fundamental values such as accountability, integrity and a winning mindset
Full description
Job Details:
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Job Description:
From the IoT to the data center, Altera offers a broad portfolio of programmable logic solutions that allow customers to solve a wide variety of system level challenges.
- Be part of the talented PCIe IP design verification team
- We are looking for experienced IP design verification engineer
Responsibility includes
Create comprehensive verification plan based on FPGA IP architecture specifications and carry out all the IP verification tasks. Developing IP, subsystem or system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Review verification and validation results against the coverage goals. Writing, analysing and achieving coverage metrics with failures debugging as well as bug filling and closure. Interfacing with 3rd party vendors for latest industry tool and methodology or VIP exposure and evaluation Understanding and enhancement of Design Verification processes in the FPGA development flow Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time to market. Provide practical, innovative solutions to complex problems.
This role requires excellent communication and leadership skills and a proven ability to work with challenging schedules. Join our team of innovators to push the boundaries of what’s possible and move into the future.
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Qualifications:
- MSEE/BSEE or equivalent with 5 years of experience in IP / SoC design verification.
- Strong in System Verilog, UVM, Verilog
- Strong in coverage-based verification methodology with assertions
- Knowledge on PCIe is a must
- Familiar with Perl, Python, Java is a plus
- Familiarity with Intel Quartus or Xilinx Vivado is a plus.
- Strong skills in communication, initiative, promote innovation and teamwork
- Highly motivated to learn and adapt to fast changing technologies and environments
- Demonstrates fundamental values such as accountability, integrity and a winning mindset
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Job Type:
Regular
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Shift:
Shift 1 (India)
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Primary Location:
Bengaluru, Karnataka, India
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Additional Locations:
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