Full-Chip Physical Design Verification Engineer
Full-chip physical design verification engineer ensuring manufacturable silicon for AI SoCs using DRC/LVS/ERC flows and advanced nodes (7nm–3nm).
- Compensation
- $100K–$500K / yr
- Location
- Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Full time
- Experience
- 7+ years
- Category
- Design
- Posted
Skills
Must have
- A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
- A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
- A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
- A mentor and technical leader passionate about building efficient, manufacturable silicon.
Full description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you.
This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
- A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
- A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
- A mentor and technical leader passionate about building efficient, manufacturable silicon.
What We Need
- BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.
- Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
- Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
- Scripting proficiency in Python and TCL for automation and flow optimization.
What You Will Learn
- Advanced physical verification methodologies and flow optimization for next-generation SoCs.
- Integration and verification strategies for full-chip signoff across advanced process technologies.