Functional Safety Architect

Job Details:

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Job Description:About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking a Functional Safety Architect to lead and oversee the functional safety activities across various semiconductor and IP development projects for Avionics, Space, Defense, Automotive, and Industrial market segment. In this role, you will own the device safety architecture and lead the efforts to achieve safety goals by developing technical safety concepts including safety mechanisms derived from safety analyses; and allocating decomposed safety requirements to each IP sub-blocks for next-generation semiconductor devices.

You will collaborate with architects, IP owners, RTL design engineers, physical design, firmware and verification teams to deliver critical safety collaterals ensuring end goal of achieving successful functional safety certification.

Additional responsibilities may include ensuring process and product compliance with ISO 26262, IEC 61508, and other relevant safety standards such as DO-254/DO-178, collaborating with internal teams and external stakeholders to demonstrate systematic capability throughout the safety lifecycle. As a technical leader, you will drive engineering teams toward the successful delivery of safety rated devices and IPs for our customers.

Become a member of our world-class SoC architecture and development team!

Key Responsibilities

• Collaborate with the Architects, Silicon Design, Software teams to architect new safety concepts and safety mechanism features and guide future development.

• Perform safety analyses (FTA, FMEA, DFA methodologies) against CCF, CF to ensure FFI, independence & Fault tolerance requirements are met.

• Define safety architecture techniques (lockstep CPUs, ECC memories, watchdogs, redundancy).

• Review and contribute to writing safety requirement specifications with FSEs.

• Guide teams on ASIL/SIL decomposition, fault tolerance, diagnostics coverage, etc.

• Review hardware/software safety designs for compliance and feasibility.

• Collaborate with design verification teams to define safety V&V strategy (fault injection, fault simulation, test methodologies).