Hardware Engineer - ASIC/SoC Physical Design

Hardware Engineer (General) ASIC/SoC Physical Design

Location: Bangalore Preferred

Secondary Location: Hyderabad Considered for exceptionally strong profiles

Work Mode: Onsite 5 Days

Experience: 10+ Years

Education: B.E./B.Tech/M.E./M.Tech

Shift: Regular

Interview Process: 2 Rounds F2F; both rounds on the same day

Role Overview:

We are looking for an experienced Hardware Engineer with 10+ years of strong hands-on experience in ASIC/SoC Physical Design, Static Timing Analysis (STA), and physical implementation flows. The ideal candidate will have proven experience owning the end-to-end physical design and signoff of complex SoC/IP tiles, from floorplanning through final signoff, while driving timing, power, area, congestion, and physical verification closure.

Key Responsibilities:

• Own end-to-end physical design implementation of SoC/IP tiles, from floorplan through signoff.

• Perform and drive Static Timing Analysis (STA) and timing closure activities.

• Drive closure of timing, power, area, congestion, and physical verification (PV) requirements.

• Debug complex physical implementation issues and identify root causes.

• Collaborate closely with Front-End (FE), Functional/FCNL, Clock, Power, and Physical Verification (PV) teams for design convergence.

• Work on physical implementation flows including placement, clock tree synthesis, routing, optimization, and signoff.

• Develop and maintain automation scripts and productivity tools to improve implementation efficiency.

• Lead execution of critical design tiles and ensure project milestones are achieved.

• Provide technical guidance and mentorship to junior engineers.

• Contribute to improving PD methodologies, flows, and design quality.

Must-Have Skills:

• 10+ years of hands-on experience in ASIC/SoC Physical Design and/or STA.

• Strong experience in physical implementation flows.

• Proven ownership of end-to-end PD execution from floorplan to signoff.

• Strong understanding of timing closure and STA.

• Experience driving PPA, congestion, timing, and physical verification closure.

• Strong debugging and problem-solving skills.

• Experience working with cross-functional teams including FE, Clock, Power, and PV.

• Scripting/automation experience for improving PD productivity.

• Ability to lead critical blocks/tiles and mentor junior engineers.

Preferred Experience:

• Experience with complex SoC/IP physical design.

• Strong understanding of advanced-node implementation challenges.

• Experience with industry-standard Synopsys/Cadence physical design and signoff tools.

• Experience in developing automation for physical design flows.

Candidate Profile:

We are looking for a technically strong Senior/Lead-level ASIC Physical Design Engineer who can independently own critical design areas, drive closure, solve complex implementation challenges, and provide technical leadership to the team.