Experience validating server, AI, networking, or accelerator platforms.
Experience with PCIe, Ethernet, UALink, or other high-speed interface compliance and interoperability testing.
Experience developing automated validation frameworks and data analysis workflows.
Contributions to technical publications, patents, industry standards, or internal best-known methods (BKMs).
Experience validating server, AI, networking, or accelerator platforms.
Experience with PCIe, Ethernet, UALink, or other high-speed interface compliance and interoperability testing.
Experience developing automated validation frameworks and data analysis workflows.
Contributions to technical publications, patents, industry standards, or internal best-known methods (BKMs).
Full description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE
The High-Speed IO (HSIO) Validation Engineer is responsible for validating and debugging high-speed interfaces across CPU and GPU platforms spanning data center servers and AI systems. In this role, you will work closely with PHY design, SI/PI, firmware, and platform teams to execute validation plans, characterize interface performance, and drive root-cause analysis of silicon- and system-level issues. You will play a key role in ensuring product quality and readiness for industry-leading technologies.
WHAT YOU WILL BE DOING
Execute validation plans for high-speed IO interfaces such as PCIe Gen5/Gen6/Gen7, UALink, xGMI, Ethernet, and other emerging technologies.
Support post-silicon bring-up, characterization, compliance testing, margining, and interoperability validation across multiple platforms.
Collaborate with design, architecture, firmware, board, and test teams to investigate and resolve high-speed interface issues.
Develop and enhance test automation, validation scripts, and data analysis tools to improve validation efficiency and coverage.
Perform electrical- and protocol-level debug using oscilloscopes, BERTs, protocol analyzers, and other lab equipment.
Analyze signal integrity, power integrity, and link training behavior to identify root causes and drive corrective actions.
Document validation findings, debug results, and recommendations, and communicate status to project stakeholders.
Contribute to the continuous improvement of validation methodologies, best-known methods (BKMs), and lab infrastructure.
WHO WE ARE LOOKING FOR
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field with 5+ years of experience in high-speed IO, silicon validation, system validation, or related areas.
Experience with high-speed serial interfaces such as PCIe, CXL, Ethernet, UALink, or similar technologies.
Strong understanding of signal integrity concepts, channel characteristics, equalization techniques (CTLE, DFE, TX FIR), and link-level behavior.
Experience with lab bring-up, validation, and debug using high-speed measurement equipment such as oscilloscopes, BERTs, VNAs, and protocol analyzers.
High Speed IO Validation Engineer at AMD (Santa Clara, CA, United States) — aijobsearch
Strong programming and scripting skills in Python, C/C++, or similar languages for automation and data analysis.
Familiarity with silicon bring-up, compliance testing, and system-level debug methodologies.
Strong analytical and problem-solving skills with the ability to drive technical issues to resolution.
Effective communication and collaboration skills within cross-functional engineering teams.
PREFERRED QUALIFICATIONS
Experience validating server, AI, networking, or accelerator platforms.
Experience with PCIe, Ethernet, UALink, or other high-speed interface compliance and interoperability testing.
Experience developing automated validation frameworks and data analysis workflows.
Contributions to technical publications, patents, industry standards, or internal best-known methods (BKMs).
Strong commitment to quality, innovation, teamwork, and continuous improvement.
ACADEMIC CREDENTIALS:
Bachelor’s, Master’s or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
Location
Santa Clara, CA
This role is not eligible for visa sponsorship.
#LI-LM1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE
The High-Speed IO (HSIO) Validation Engineer is responsible for validating and debugging high-speed interfaces across CPU and GPU platforms spanning data center servers and AI systems. In this role, you will work closely with PHY design, SI/PI, firmware, and platform teams to execute validation plans, characterize interface performance, and drive root-cause analysis of silicon- and system-level issues. You will play a key role in ensuring product quality and readiness for industry-leading technologies.
WHAT YOU WILL BE DOING
Execute validation plans for high-speed IO interfaces such as PCIe Gen5/Gen6/Gen7, UALink, xGMI, Ethernet, and other emerging technologies.
Support post-silicon bring-up, characterization, compliance testing, margining, and interoperability validation across multiple platforms.
Collaborate with design, architecture, firmware, board, and test teams to investigate and resolve high-speed interface issues.
Develop and enhance test automation, validation scripts, and data analysis tools to improve validation efficiency and coverage.
Perform electrical- and protocol-level debug using oscilloscopes, BERTs, protocol analyzers, and other lab equipment.
Analyze signal integrity, power integrity, and link training behavior to identify root causes and drive corrective actions.
Document validation findings, debug results, and recommendations, and communicate status to project stakeholders.
Contribute to the continuous improvement of validation methodologies, best-known methods (BKMs), and lab infrastructure.
WHO WE ARE LOOKING FOR
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field with 5+ years of experience in high-speed IO, silicon validation, system validation, or related areas.
Experience with high-speed serial interfaces such as PCIe, CXL, Ethernet, UALink, or similar technologies.
Strong understanding of signal integrity concepts, channel characteristics, equalization techniques (CTLE, DFE, TX FIR), and link-level behavior.
Experience with lab bring-up, validation, and debug using high-speed measurement equipment such as oscilloscopes, BERTs, VNAs, and protocol analyzers.
Strong programming and scripting skills in Python, C/C++, or similar languages for automation and data analysis.
Familiarity with silicon bring-up, compliance testing, and system-level debug methodologies.
Strong analytical and problem-solving skills with the ability to drive technical issues to resolution.
Effective communication and collaboration skills within cross-functional engineering teams.
PREFERRED QUALIFICATIONS
Experience validating server, AI, networking, or accelerator platforms.
Experience with PCIe, Ethernet, UALink, or other high-speed interface compliance and interoperability testing.
Experience developing automated validation frameworks and data analysis workflows.
Contributions to technical publications, patents, industry standards, or internal best-known methods (BKMs).
Strong commitment to quality, innovation, teamwork, and continuous improvement.
ACADEMIC CREDENTIALS:
Bachelor’s, Master’s or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
Location
Santa Clara, CA
This role is not eligible for visa sponsorship.
#LI-LM1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Tags: No, USD $143,500.00/Yr., USD $205,000.00/Yr., US Careers (External)