High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei)
- Compensation
- Not disclosed
- Location
- Hsinchu City, Taiwan
- Work setup
- Onsite
- Seniority
- Staff
- Employment
- Not specified
- Experience
- 4+ years
- Category
- Software engineering
- Posted
Skills
Must have
- Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of hands-on experience in RTL design and SoC integration
- Proficiency in Verilog/SystemVerilog and RTL design methodologies
- Experience with integration and performance evaluation of USB / PCIe / UHS 3rd party IPs
- Familiarity with RTL-to-GDSII flow and timing closure
- Strong scripting skills in Python, Tcl, or Shell
- Excellent problem-solving and cross-functional communication skills
- Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committ
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Nice to have
- Experience with low-power design techniques and clock/power domain crossing
- Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design
- Familiarity with post-silicon validation and debug of interface IPs
- Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools
- Comfortable working in a globally distributed engineering environment
- Experience correlating pre-silicon verification with post-silicon performance/yield
Full description
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Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.
We are seeking a seasoned RTL Design Engineer to join our SoC design team. In this role, you will be responsible for architecting and implementing RTL designs for complex SoC platforms, with a focus on integration and performance evaluation of 3rd party IPs such as USB and PCIe. You will collaborate closely with verification, physical design, and system architecture teams to ensure seamless integration, robust functionality, and optimal performance.
Responsibilities
- Define and implement RTL architecture for SoC subsystems
- Integrate 3rd party IPs (USB, PCIe, UHS) into SoC designs and evaluate their performance
- Develop and optimize RTL code for performance, power, and area efficiency
- Collaborate with verification teams to ensure functional correctness and coverage
- Work with physical design teams to achieve timing closure and DFT compliance
- Debug and resolve RTL issues across simulation, emulation, and silicon validation
- Drive methodology improvements and automation for RTL design flow
- Provide guidance on coding styles, interface protocols, and best practices
- Occasional business travel across APAC and other regions may be required
Minimum Qualifications
- Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of hands-on experience in RTL design and SoC integration
- Proficiency in Verilog/SystemVerilog and RTL design methodologies
- Experience with integration and performance evaluation of USB / PCIe / UHS 3rd party IPs
- Familiarity with RTL-to-GDSII flow and timing closure
- Strong scripting skills in Python, Tcl, or Shell
- Excellent problem-solving and cross-functional communication skills
Preferred Qualifications
- Experience with low-power design techniques and clock/power domain crossing
- Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design