[India] SOC RTL Integration Engineer

Introduction

We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team.

The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to synthesis, timing constraints, implementing ECOs, STA, Power intent implementation & validation, lint, power analysis, CDC RDC Analysis & Validation. You will also model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures and contribute to implementation methodologies and flows.

Specific responsibilities will be a function of project and team needs and may vary over time. In addition to implementation tasks the successful candidate may also be asked to perform ASIC design tasks including some RTL development, or physical design activities from floor plan definition to P&R and participate in creative problem solving as part of a crossdisciplinary design team.

About Edgecortix

At Edgecortix we are a deep-tech startup revolutionizing edge computing with artificial intelligence and novel high efficiency silicon on chip design. Originating from multiple years of research, our unique AI hardware & software co-design principle and the Dynamic Neural Accelerator ® AI processor IP are geared towards positively disrupting the rapidly growing artificial intelligence edge hardware space and bring the power of AI and machine learning to all kinds of devices. Our operations are headquartered in Tokyo, Japan, with offices in Singapore, Virginia, California in the US. In addition, we are starting a new Design Center in India, located in Hyderabad.

The Team

As an engineering driven company we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy-efficiency for AI inference at the edge.

Role and Responsibilities

As the Senior SoC Engineer, you would be responsible for development and execution of SOC RTL Design, Integration, and related RTL design checks, participate and contribute to architecture discussions, work with DFT, Verification and Physical Design teams.

The role will involve owning parts of the SOC design (one or more subsystem, full-chip level design activities) and plan its deliverables in line with the overall project deliverables. Role requires hands-on-experience in all aspects and stages of Design, frontend, DFT, and Verification. Chip level aspects like Clocking, Booting, Low power design. PPA analysis, IP evaluations and selection are integral part of the job scope. Engagement and collaboration across the global teams is a key aspect of this role. Strong technical, analytical skills combined with strong communication, and consensus building skills are required. Senior SoC Engineer will partner with other design leads, architects and adhere to the best practices across all teams. A zero-defect, total quality mindset is a key enabler.