MediaTek 聯發科技
interconnect fabric design and system level cache IP engineer
- Compensation
- Not disclosed
- Location
- Hsinchu, Hsinchu City, Taiwan
- Work setup
- Onsite
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Design
- Posted
Full description
- Interconnect IP/Fabric IP/System-level-cache IP/related bus-subsys design for different products (smartphone/AUTO/...)
- Cowork with DV team to secure functionality
- Cowork with performance validation team to secure performance requirement (BW/latency) is met
- IP Design Quality Control flow execution (lint, CDC, spyglass DFT, UPF,...)
- RTL Front-End flow execution (SDC quality check, clock constraint check, ...)
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