Lead Principal Engineer, Layout Design
- Compensation
- Not disclosed
- Location
- Tlaquepaque, Jalisco, Mexico
- Work setup
- Onsite
- Seniority
- Principal
- Employment
- Not specified
- Experience
- 10+ years
- Category
- Design
- Posted
Skills
Must have
- 10+ years of experience in the Semiconductor industry.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
- Strong understanding of CMOS devices and layout-dependent effects.
- Hands-on experience with custom IC layout and physical verification tools.
- Comprehensive understanding of reliability checks and layout constraints.
- Experience leading technical execution and delivering tapeouts.
- Proficiency in scripting/automation to improve layout efficiency.
Nice to have
- Master's Degree or PhD in Electrical/Computer Engineering or related field, or equivalent experience in lieu of either degree.
- Excellent problem-solving and debug skills.
- Self-motivated and diligent with the ability to prioritize multiple tasks.
- In-depth knowledge of advanced-node layout considerations and memory/storage technology trends.
- Strong communication skills to align constraints and tradeoffs.
Full description
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build.
Key Responsibilities
- Lead the layout build and physical realization of new memory products.
- Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets.
- Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools.
- Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability.
- Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing.
- Produce layout collateral and documentation for cross-team integration.
Physical Verification and Tapeout Signoff
- Run and debug physical verification flows and ensure closure using industry tools.
- Perform parasitic extraction and work with circuit designers to assess impact on timing, power, noise, and functionality.
- Resolve layout issues related to signal integrity, coupling/crosstalk, antenna effects, and power integrity.
Technical Expertise and Training
- Drive standard physical build practices and maintain layout documentation.
- Participate in continuing education on advanced nodes and industry trends.
- Solicit feedback from various groups to ensure layout quality and tool-flow robustness.
- Innovate for future memory generations through layout-centric optimizations and improved methodologies.
Project Management
- Lead resource planning, priorities, and tapeout schedules across multiple blocks.
- Serve as the contact for layout implementation, physical verification, PEX/signoff, and integration issues.
- Track closure of achievements and coordinate ECO execution to meet tapeout landmarks.