Lead RTL Design Engineer
Lead the RTL design and microarchitecture of an ultra-low-power SoC for edge AI/IoT, defining dataflow fabrics, memory subsystems, and interconnects using SystemVerilog and collaborating across hardware, firmware, and verification teams.
- Compensation
- $160K–$250K / yr
- Location
- San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
- Work setup
- Not specified
- Seniority
- Lead
- Employment
- Not specified
- Experience
- 8+ years
- Category
- Hardware
- Posted
Skills
Must have
- 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator SoC.
- Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch.
- Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer
- Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.
- Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
- Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.
- Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries.
- Strong written communication skills; able to produce uArch specs and design review material independently.
- Experience with memory compiler toolchains
Nice to have
- Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management.
- Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations.
- Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases.
- Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and the RTL design choices they necessitate.
- Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation.
- Exposure to AI framework graph formats (ONNX, TFLite) and understanding of how graph compilation maps to hardware execution primitives.
- Tape-out credits on an edge-AI, IoT, or wearable SoC at 12nm or below.
- Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance.
Full description
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.
We are looking for a Lead RTL Design Engineer to own microarchitecture definition and RTL implementation across the dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP (RiscV, NVM, I2S, I2C) integration. You will work from architecture spec through synthesis-ready RTL, collaborating with architects, microarchitects, DV leads, physical design, and firmware teams to tape out an industry leading power-efficient SoC.
This is a unique opportunity to be a part of a newly formed HW engineering org and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key Responsibilities
- Microarchitecture definition (core focus): Own the design and definition of processor and compute-unit microarchitecture, including dataflow pipelines, execution units, and interfaces. Set performance, power, and area targets, and guide the team toward achieving them.
- On-chip interconnects and system integration: Define and drive the design of on-chip networks and data movement across the fabric, balancing performance, scalability, and implementation constraints in collaboration with physical design.
- Memory subsystem & system architecture: Define the interface to the memory subsystem, including data movement, ordering, and synchronization behavior, ensuring a clean and scalable model for software and future system expansion.
- Reconfiguration and execution model: Lead the architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and interaction with host systems.
- Power management and low-power design: Drive power architecture across the design, including clocking, reset, power domains, and low-power strategies to meet aggressive energy and efficiency goals.