Logic Design Engineer

Job Details:

Job Description:

The Role and Impact :
Join Intel as an SoC Logic Design Engineer, where you will play a pivotal role in developing the logic design for Intel's next-generation Client System-on-Chip (SoC) products. You will contribute to the RTL design, integration of high-performance IPs, and optimization of core functionalities, ensuring world-class technology that powers devices globally. Your work will directly influence product innovation and performance, driving advancements in computing technology.

Business group :
This role is part of the Silicon and Platform Engineering Group (SPE), which focuses on developing cutting-edge semiconductor solutions and delivering world-class silicon products. SPE drives innovation in Client SoCs by integrating advanced IPs and ensuring high-quality functionality to support Intel's mission of creating technology that enriches lives and shapes the future of computing.

Key Responsibilities :

• Develop RTL designs for internal IPs or integrate high-performance, bandwidth IPs into SoCs.
• Collaborate with verification teams to ensure functional, feature, and integration validation.
• Perform quality checks across RTL static analysis, synthesizability assessments, timing/power convergence, netlist quality verification, and functional equivalence validation.
• Work with design teams and architects to ensure functional integrity, performance, and overall chip quality.
• Provide innovative solutions for design optimization and contribute to cross-functional reviews.
• Follow secure development practices to address security threat models and meet design integrity standards.
• Collaborate with IP providers to integrate and validate IPs at the SoC level, ensuring smooth IP/SoC handoff.

Qualifications:

Minimum Qualifications :

• Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of hands-on experience in SoC RTL/Logic Design, demonstrated through internships, academic projects, coursework, or hands-on training OR a Master's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field with no prior professional experience.
• Proficiency in RTL design languages such as SystemVerilog.
• Basic understanding of digital design concepts, including timing analysis, power optimization, and synthesis techniques.
• Familiarity with verification methodologies such as OVM/UVM.

Preferred Qualifications :

• Experience with logic design, integration of high-performance IPs, or pre-silicon validation environments.
• Knowledge of industry-standard tools for RTL simulation, synthesis, and static timing analysis.