Logic Design Engineer - RTL/DFT

Job Title : Logic Design Engineer Core Instruction Sequencing Unit - Bangalore

Location : Bangalore, Karnataka

Experience : 8-20 Years

Industry : Semiconductor - Hardware Design

About the Role :

We are looking for experienced Logic Design Engineers to join the Processor Development team and contribute to the design of next-generation high-performance CPUs. In this role, you will be responsible for architecting and developing the Instruction Sequencing Unit (ISU) and driving the complete RTL design lifecycle from microarchitecture to silicon validation.

Key Responsibilities :

• Lead the design and development of the Instruction Sequencing Unit (ISU) for high-performance processor CPUs.

• Architect and implement Instruction Dispatch, Issue Queues, Register Renaming, Out-of-Order (OoO) Execution, and Reorder Buffers (ROB).

• Develop microarchitecture and RTL for processor core features.

• Participate in architecture discussions and present high-level design proposals.

• Estimate implementation effort, silicon area, timing, and wire usage for new features.

• Collaborate with Verification, DFT, Physical Design, Timing, Firmware, and Software teams throughout the development cycle.

• Ensure pre-silicon design signoff meets functional, timing, and area goals.

• Support post-silicon bring-up, debugging, and hardware validation.

• Lead design reviews, mentor engineers, and represent the team in global technical forums.

Required Skills :

• Strong experience in CPU/Processor Logic Design.

• Expertise in Microarchitecture and RTL Design (Verilog/SystemVerilog).

• Hands-on experience with :

• Instruction Sequencing Unit (ISU)

• Instruction Dispatch

• Register Renaming

• Out-of-Order (OoO) Execution

• Issue Queues

• Reorder Buffers (ROB)

• Execution Pipelines

• Strong understanding of Processor Architecture and High-Performance CPU Design.

• Experience with Functional Verification, DFT, Timing Closure, and Physical Design collaboration.

• Knowledge of Pre-Silicon and Post-Silicon Validation.

• Excellent debugging, analytical, and problem-solving skills.

Preferred Skills :

• Experience in ASIC/SoC Design.

• Familiarity with Cadence, Synopsys, or Siemens EDA tools.

• Scripting knowledge in Python, Perl, Tcl, or Shell.

• Experience leading technical teams and mentoring engineers.

Preferred Background :

• Candidates from leading semiconductor companies such as IBM, Intel, AMD, Qualcomm, NVIDIA, Arm, Broadcom, Marvell, MediaTek, Samsung Semiconductor, Texas Instruments, Synopsys, SiFive, or similar organizations are encouraged to apply.