Manager Design Verification
A technical manager role at Astera Labs in Tel Aviv owning RTL design execution for connectivity silicon blocks that power large AI clusters — taking features from microarchitecture through synthesis, timing closure, and tapeout using Verilog/SystemVerilog with PCIe, CXL, and Ethernet interconnect technologies.
- Compensation
- Not disclosed
- Location
- Tel Aviv-Yafo, Tel Aviv District, Israel
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 4+ years
- Category
- Design
- Posted
Skills
Must have
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of digital design experience, including at least one full chip from spec to tapeout
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
- Familiarity with formal verification, emulation, or assertion-based methodologies
- Background in advanced process nodes (7nm, 5nm, or below)
- Strong debug skills across pre-silicon and post-silicon environments
Full description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .
Manager Design VerificationTel Aviv District, Israel
Astera Labs is seeking an experienced Manager, Design Verification to lead a team responsible for verifying the next generation of connectivity silicon powering the world's largest AI clusters. In this role, you will drive verification strategy and execution for complex SoC and IP designs supporting PCIe, CXL, Ethernet, UALink, and other advanced interconnect technologies.
You will partner closely with Architecture, Design, Firmware, Post-Silicon Validation, and Program Management teams to ensure first-pass silicon success while scaling methodologies and processes across a growing organization.
Key ResponsibilitiesVerification Leadership
- Lead and mentor a team of Design Verification engineers.
- Define verification strategies, schedules, and execution plans for IP, subsystem, and SoC-level verification.
- Drive verification planning, resource allocation, and project execution to meet aggressive tapeout schedules.
Verification Development & Execution
- Own verification sign-off criteria, coverage metrics, and quality standards.
- Develop and review UVM/SystemVerilog testbenches, checkers, scoreboards, and verification components.
- Collaborate with Design and Architecture teams to ensure comprehensive verification of specifications and microarchitectures.
Methodology & Quality
- Establish and improve verification methodologies, infrastructure, and best practices.
- Establish reusable verification frameworks across multiple projects.
- Ensure high-quality metrics-driven verification sign-off.
Cross-Functional Collaboration
- Work closely with RTL Design, DFT, Firmware, Post-Silicon Validation, and Physical Design teams.
- Support bring-up and debug activities by correlating pre-silicon and post-silicon results.