Realtek
Memory Compiler Application Engineer
Application engineer at Realtek (Hsinchu) doing quality verification and support for memory compiler silicon IP — validating front-end/back-end models (Verilog, Liberty, LEF, SPICE), physical-verification flows (DRC/LVS/ERC/RCX), and simulation/layout tools (Hspice, Spectre, Virtuoso), with scripting automation in Python/TCL/Shell.
- Compensation
- Not disclosed
- Location
- Hsinchu
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- Not specified
- Category
- Industrial engineering
- Posted
Skills
Must have
- Master's degree or above in Electrical Engineering, Electronics, Computer Science or related fields
- Familiar with front-end & back-end models including Verilog, Liberty (NLDM/CCS/LVF), DFT, RedHawk, LEF, SPICE view
- Familiar with physical verification flows including DRC, ERC, LVS, RC extraction
- Familiar with Hspice, Spectre, Solido simulation tools and Virtuoso, Laker layout tools
- Familiar with scripting languages: Python/Verilog/TCL/Shell/Makefile/C
Nice to have
- Familiar with SRAM operating principles and bit cell characteristics
- Experience in SRAM failure/error analysis and yield improvement
- Experience with silicon IP contract management
Full description
工作項目：
Memory Compiler quality verification and support。
應徵條件：
- 碩士以上; 電機、電子、資工相關科系畢業為主。
- Familiar with front-end & back-end model including verilog, liberty (nldm/ccs/lvf), dft, redhawk, lef, spice view。
- Familiar with physical verification flows including drc, erc, lvs, rc extraction。
- Familiar with Hspice, Spectre, Solido simulation tool & Virtuso, Laker layout tool。
- Familiar with Scripting language: Python/Verilog/TCL/Shell/Makefile/C。
- 具以下條件者佳：
(1) 熟悉SRAM操作原理及bit cell特性。
(2) 從事SRAM錯誤分析及良率改善。
(3) 具矽智財合約管理經驗。