Microarchitect / RTL Design - Interconnect & Fabric
Design and own the on-chip interconnect fabric and high-speed I/O subsystems for AI-driven ASICs, implementing AMBA-compliant NoC routers, crossbars, and bridges to ensure low-latency, high-bandwidth data movement in production silicon.
- Compensation
- Not disclosed
- Location
- Palo Alto
- Work setup
- Onsite
- Seniority
- Principal
- Employment
- Not specified
- Experience
- Not specified
- Category
- Design
- Posted
Skills
Must have
- Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
- AMBA Protocol Expertise: Deep familiarity with ARM AMBA protocol suite — AXI4/AXI5 (channel mechanics, burst types, ordering, exclusive access), ACE/ACE-Lite (coherence transactions, snoop channels),
- NoC/Fabric Design: Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects including arbitration schemes (round-robin, priority, age-based, bandwidth-regul
- High-Speed I/O Integration: Experience with HSIO bridge logic — PCIe root complex/endpoint bridge design, protocol translation, or custom chip-to-chip links (UCIe, proprietary die-to-die) including li
- Peer-to-Peer Data Movement: Experience with peer-to-peer DMA architectures, zero-copy data transfer engines, scatter-gather descriptors, and direct device-to-device communication paths that bypass hos
- SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits — parameterization for configurable port counts and data widths, modularity for hierarchical fabric composition, and confi
- SoC Methodology: Solid grasp of synthesis, timing constraints (especially for wide crossbar paths and high-radix switches), clock domain crossings (fabric-to-IP clock boundaries, async bridge design),
- Python: Strong skills for design automation, traffic generation/analysis, NoC configuration scripting, regression infrastructure, and tooling.
- PPA Ownership: Experience taking an interconnect or fabric block from RTL through synthesis and working with PD teams on timing/area/power closure — particularly for wide-datapath crossbars and high-f
Nice to have
- Experience with coherent multi-chip/multi-die interconnect architectures (chiplet-based designs, UCIe, BoW).
- Familiarity with hardware coherence protocols: MOESI/MESIF state machines, snoop filter design, directory-based coherence.
- Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis.
- Low-power design techniques for interconnect: clock gating idle ports, power gating unused links, link-level power states (L0s/L1), dynamic frequency/width scaling.
- FPGA prototyping experience (Xilinx Vivado/Vitis), especially with AXI interconnect IPs, NoC IPs (Versal), or custom fabric implementations.
- SVA assertions for protocol compliance: AXI ordering rules, CHI transaction flows, deadlock detection, and livelock/starvation monitors.
- Prior IP building and delivery experience for NoC IPs, AXI interconnect IPs, PCIe controllers, or CXL endpoint/switch IPs.
- Performance modeling: experience building or using NoC simulators (e.g., BookSim, Garnet) or system-level traffic models to validate fabric microarchitecture.
- Domain-specific research contributions: publications or patents in on-chip networks, interconnect architectures, or high-performance data movement for ML/HPC workloads.
Full description
About Architect Labs
Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.
What You’ll Do
As a Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of the on-chip interconnect fabric and high-speed I/O data movement subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for NoC routers, crossbar switches, high-speed fabric bridges, and peer-to-peer data transfer engines — ensuring low-latency, high-bandwidth, and deadlock-free communication across all SoC agents.
Core Responsibilities
- Own the on-chip fabric RTL end-to-end: from NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
- Design and implement AMBA-based interconnect fabrics: including AXI/ACE/CHI-compliant crossbar switches, network interfaces (NIs), protocol converters (AXI-to-CHI bridges, AXI-to-AHB/APB downconverters), and multi-layer interconnect configurations optimized for ML accelerator traffic patterns.
- Architect NoC routers and topologies: including virtual-channel routers, wormhole/flit-based switching, adaptive routing algorithms, QoS-aware arbitration (bandwidth regulation, latency-critical path prioritization), and deadlock-free network design for mesh/ring/tree topologies.
- Design high-speed I/O fabric bridges and peer-to-peer engines: including PCIe/CXL-to-fabric bridges, chip-to-chip interconnect logic (UCIe, custom die-to-die links), peer-to-peer DMA controllers for direct device-to-device transfers bypassing host memory, and coherent/non-coherent multi-chip fabric extensions.
- Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (latency vs. bandwidth vs. area, coherence overhead vs. performance), and feed area/timing/power realities back into the architecture and internal AI systems.
- Define and maintain interface specifications: AMBA AXI4/AXI5, ACE/ACE-Lite, CHI (with snoop filter interfaces), AXI-Stream for streaming datapaths, custom sideband channels for QoS/ordering, and high-speed SerDes-facing interfaces for off-chip links.