Packaging Process Engineer - Singapore

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip.

Key Responsibilities

• Process Integration Management : Serve as the sole interface between internal teams and OSATs, fabs, and substrate vendors to resolve process-related issues for 2D/2.5D/3D packaging projects.
• Project Execution & Risk Control : Follow up with suppliers to meet process requirements, intervene in problem-solving, and ensure smooth production flow.
• R&D Pre-research : For advanced R&D projects, lead process research, drive vendors to meet technical requirements, and conduct pre-verification of new packaging technologies.
• Cross-team Collaboration : Coordinate with packaging design, thermal/stress simulation, and product teams to align process constraints and resolve cross-domain technical issues.

Minimum Qualification(s)

• Master's degree or above in Microelectronics, Electronics, Materials Science, Mechanical Engineering, or related fields, with at least 2 years of relevant work experience.
• Proven experience in 2D/2.5D/3D packaging process integration , with hands-on experience in at least one of the following packaging technologies: FCBGA, FCCSP, MCM, 2.5D, 3D.
• Familiar with packaging process flow, process design rules (DRM).
• Proficient in process problem-solving methodologies, with experience in leading root cause analysis and corrective action implementation for packaging process failures.
• Strong cross-team communication skills.

Preferred Qualification(s)

• Experience in mass production process integration for 2.5D or 3D packaging (TSV bonding, 3D stacking) projects.
• Experience in process optimization for advanced packaging technologies.
• Familiar with packaging reliability verification standards and thermal/stress simulation basics.