PD Partition Lead (Physical Design, Semiconductors)
Semiconductor physical-design lead at Capgemini Engineering in Katowice, owning full-chip/block-level implementation at advanced nodes (10nm and below): floorplanning, partitioning, power planning, CTS, place-and-route, timing/ECO closure, sign-off checks (DRC/LVS/EM/IR), and Perl/TCL/Python scripting, with the chance to lead other PD engineers.
- Compensation
- Not disclosed
- Location
- Katowice, PL
- Work setup
- Hybrid
- Seniority
- Lead
- Employment
- Not specified
- Experience
- Not specified
- Category
- Design
- Posted
Skills
Must have
- Good knowledge of synthesis flow, insertDFT scan/coverage and optimization
- Excellent floorplan, power plan, CTS, place, route, and timing closure skills
- Proficiency using Perl/TCL/Python scripting and Makefile
- Expertise in timing STA/PTSI - signal integrity closure, ECO generation/implementation
- Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills
- Experience with sign-off tape-out closure work
Nice to have
- Partitioning experience
- Experience leading/tech leading small teams
Full description
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At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.
Your role
Are you in search for a new challenge? We are looking for Physical Design expert with experience in partitioning who dreams about becoming a Lead or Tech Lead for new, exciting projects!
Take the opportunity and join us as a PD Partitioning Lead!
Your tasks
- Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);
- In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;
- Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);
- In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;
- Be part of the overall Low Power solution development and implementation;
- Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);
- Complete multiple design cycles of high complexity with little supervision.
- Possiblity to lead other PD Engineers.
Your profile
- Good knowledge of synthesis flow, insertDFT scan/coverage and optimization;
- Excellent floorplan, power plan, CTS, place, route, and timing closure skills;
- Proficiency using Perl/TCL/Python scripting and Makefile;
- Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;
- Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;
- Experience with sign-off tape-out closure work;
- Partitioning experience is a plus;
- Experience in leading/tech leading small teams will be a plus.
What You'll love about working here
- Well-being culture: medical care with Medicover, private life insurance, and sports card. But we went one step further by creating our own Capgemini Helpline offering therapeutical support if needed and the educational podcast "Let's talk about wellbeing" which you can listen to on Spotify.