Performance Modeling Architect
CPU Performance Modeling Architect at Tenstorrent building performance models to guide architectural decisions for next-generation RISC-V CPUs optimized for AI and HPC workloads, using tools like Gem5/SST and C++/Python.
- Compensation
- $100K–$500K / yr
- Location
- Austin, Texas, United States; Santa Clara, California, United States
- Work setup
- Not specified
- Seniority
- Not specified
- Employment
- Not specified
- Experience
- 8+ years
- Category
- Architecture
- Posted
Skills
Must have
- 1-5 years of industry experience or equivalent research experience in CPU architecture, performance analysis, or microarchitecture development
- Strong foundation in CPU core or mid-core design and understanding of modern processor pipelines and performance tradeoffs
- Experience working on CPU core, mid-core, or microarchitecture development through industry, research, or advanced academic projects
- Experience with performance modeling tools such as Gem5, SST, SimpleScalar, or equivalent simulation environments
- Strong programming skills in C++, Python, or similar languages used for architectural modeling and analysis
- Understanding of processor subsystems such as instruction scheduling, branch prediction, caches, memory hierarchy, prefetching, and execution pipelines
Nice to have
- PhD preferred (MS considered) in Computer Engineering, Electrical Engineering, Computer Science, or a related field
Full description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is building next-generation processors and systems, bringing together world-class expertise across silicon, systems, and software. We are looking for a CPU Performance Modeling Architect to help evaluate, shape, and optimize the performance of future CPU architectures. In this role, you’ll use performance modeling, workload analysis, and deep understanding of CPU architecture to answer complex questions about how a processor should be designed. You’ll work closely with CPU architects, RTL designers, software and compiler teams, and system engineers to identify performance opportunities, evaluate architectural tradeoffs, and turn modeling insights into actionable design decisions.
This role ishybrid, based out of Santa Clara, CA or Austin, TX.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A CPU architect, performance architect, or performance modeling engineer with experience influencing CPU architecture or microarchitecture decisions.
- You have a strong understanding of modern processor architecture and enjoy digging into why a CPU performs the way it does.
- You are comfortable combining hardware architecture, software, data, and analytical modeling to solve complex performance problems.
- You can move between high-level architectural questions and detailed analysis of CPU pipelines, memory systems, workloads, and bottlenecks.
- A strong collaborator and technical communicator who can turn complex modeling results into clear recommendations and drive decisions across engineering teams.
What We Need
- 8+ years of experience in CPU architecture, performance modeling, microarchitecture, performance analysis, or a closely related field.
- Strong understanding of CPU architecture and microarchitecture, including areas such as pipelines, execution, scheduling, branch prediction, caches, memory hierarchy, and data movement.