Physical Design Engineer - ASIC/SoC

Job Title: Physical Design (5 - 7 Years & 7+ years)

Location: Ahmedabad, Gujarat

No. of opening: 4

Company: VeriFast Technologies

This position requires a hands-on Physical Design expert with 5 - 7 years of experience implementing complex ASICs and SoCs in RT2GDS flows.

Key Responsibilities:

• Must have done at least 3 tapeouts on lower tech nodes like TSMC 7nm/5nm/3nm.

• Own complex blocks through the complete RTL-to-GDS physical implementation flow.

• Perform block-level floorplanning, power planning, synthesis, placement, clock-tree synthesis, routing, and physical optimization.

• Work on ECO implementation, STA/Timing closure, power, area, congestion, routability, DRC/LVS/ANT and other physical verification signoff.

• Work on EMIR and drive to closure.

• Analyse and Provide RTL feedback as well as routability feedback to different fullchip stakeholders.

• Proactively identify and raise implementation risks and recommend design changes before they become schedule-critical closure problems.

• Support block integration, hierarchical implementation, and full-chip assembly.

• Collaborate with STA, power-integrity, DFT, physical-verification, and signoff teams.

• Diagnose difficult timing, congestion, clocking, power, and physical-design problems.

• Mentor other engineers while remaining highly hands-on.

• Strong debugging, problem-solving, communication, and cross-functional skills are required.