Physical Design Engineer - Static Timing Analysis

Job Description :

We are looking for an experienced Physical Design / PNR Engineer with 5+ years of hands-on experience in block/full-chip physical design implementation. Candidate should have strong expertise in Floorplanning, Placement, CTS, Routing, STA, ECO, and Physical Signoff.

Key Skills Required :

• Strong experience in Physical Design / PNR flow

• Hands-on in Floorplanning, Placement, CTS, Routing, STA, ECO

• Experience in timing closure, congestion fixing, power optimization

• Knowledge in DRC/LVS, IR Drop, EM analysis

• Good exposure to ICC2 / Innovus / Fusion Compiler / PrimeTime

• Experience in advanced technology nodes is preferred

• Scripting knowledge in Tcl / Perl / Python is an added advantage

• Good debugging, analytical, and communication skills

Roles & Responsibilities:

• Execute end-to-end Physical Design flow from netlist to GDSII

• Perform floor planning, macro placement, and power grid design

• Handle placement with focus on timing and congestion optimization

• Implement Clock Tree Synthesis (CTS) to meet skew and latency targets

• Perform routing and resolve DRC and congestion issues

• Work on timing closure by fixing setup and hold violations

• Run STA using tools like Prime Time and analyze timing reports

• Perform physical signoff checks: DRC, LVS, IR drop, and EM

• Implement ECOs for post-route timing or functional fixes

• Optimize power, performance, and area (PPA)

• Use tools like ICC2, Innovus, Fusion Compiler for implementation

• Develop automation scripts using Tcl/Perl/Python and debug design issues