Physical Design Engineer (Subsystem Level) - Singapore

Team Introduction
The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip.

Responsibilities

• Own the physical implementation of a complex digital subsystem from netlist handoff through final GDS/tapeout.
• Drive the physical implementation strategy for the subsystem, including SoC-level partition cooperation and subsystem partitioning.
• Define and execute floorplanning and pin assignment.
• Drive PV/PI signoff at the subsystem level.
• Coordinate implementation activities across multiple blocks and ensure consistent methodology and QoR.

Minimum Qualifications

• BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 5+ years of experience in physical design / physical implementation.
• Experience owning complex digital subsystems from netlist to tapeout.
• Hands-on experience with industry-standard PD tools (e.g., Synopsys ICC2, Cadence Innovus).
• Experience with floorplanning, partitioning, and cross-block timing closure.

Preferred Qualifications

• Experience with 7nm/5nm/3nm/2nm or other advanced nodes.
• Experience owning complex subsystems such as CPU/GPU/NPU subsystems, NOC, or memory controllers for server-level chips.