PLL Design/ Integration Sr Staff Engineer
Senior staff engineer on AMD's AECG Fabric team who architects, integrates, and characterizes PLLs and analog/mixed-signal blocks (VCOs, charge pumps, LDOs, phase interpolators) for FPGA/adaptive SoC products on cutting-edge process nodes — including layout review, lab bring-up, and system validation with Vivado.
- Compensation
- Not disclosed
- Location
- US,CA,San Jose
- Work setup
- Not specified
- Seniority
- Staff
- Employment
- Not specified
- Experience
- Not specified
- Category
- Design
- Posted
Skills
Must have
- Solid foundation in IC design and manufacturing
- Experience with analog/digital IP integration (PLLs, LDOs, Phase Interpolators)
- Experience with chip design, silicon processes, and packaging technologies
- Strong understanding of device physics, reliability, and silicon chip manufacturing
- Experience with post-silicon validation and characterization
- Strong analytical and problem-solving skills; effective cross-team communication
Nice to have
- Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs
- Familiarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers
- Background in digital design, digital verification, and SystemVerilog modeling
- Knowledge of clock synthesis and recovery techniques (PLLs, DLLs, CDRs)
- Advanced degree (MS) in Electrical & Electronics Engineering; alternatively a BS with several years of relevant industry experience
Full description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
THE ROLE:
We are seeking a highly motivated and experienced Staff Design Engineer to join our AECG Fabric team. In this role, you will lead and contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across cutting-edge process nodes.
As an integral part of AMD's Programmable Logic Group, our global Clock/PLL team is responsible for implementing programmable clocking solutions and methodologies across AMD's expanding portfolio of Adaptive Embedded Computing products. Each new Adaptive SoC introduces a fresh set of programmable clock challenges, driven by evolving system and functional architectures, as well as the adoption of new semiconductor and packaging technologies. Our team collaborates closely with functional architecture, programmable fabric, integration, and software teams to design and deliver innovative clocking solutions — spanning new architectures, clock IPs, tools, and flows.
This position offers the opportunity to join a team of industry experts, where you will invent and implement original solutions to complex clocking challenges in some of the largest and most sophisticated SoCs in the industry.
THE PERSON:
You bring a solid foundation in IC design and manufacturing, including experience with analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies. A strong understanding of device physics, reliability, and silicon chip manufacturing is essential.
You have a passion for modern adaptive computing architectures and post-silicon validation and characterization. You thrive in collaborative environments, communicate effectively across teams, and bring strong analytical and problem-solving skills to every challenge. You are eager to learn, ready to take initiative, and excited by emerging technologies and innovation.
KEY RESPONSIBILITIES:
- Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes.
- Lead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range at product level.