Demonstrated Principal or Distinguished Engineer expertise
A minimum of 15+ years of experience in testability and DFT area for ASICs, memories, and 2.5D SiPs
Excellent knowledge of state-of-the-art DFT techniques in MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and 1687
Strong working level experiences on ASIC DFT implementation, post-silicon validation, debug, and diagnostic integration
Exposure to various semiconductor test challenges and solutions for high-performance ASICs, TSV, HBM (High Bandwidth Memory) DRAM, 2.5D, and 3D ICs
Broad experiences with ASIC suppliers, IP/EDA vendors, 2.5D SiP ecosystems partners, and contract manufacturers
Excellent communication, collaboration and program management skill set. Able to independently influence others.
Full description
Principal ASIC Test Development EngineerThis role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office.Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
Individual contributor role responsible for testability solutions of ASICs, memory, and 2.5D SiPs for Juniper’s product development and manufacturing. Includes both structured ATE-level test as well as system-level/mission-mode (functional) environments.
Roles
Responsible for developing test strategy and DFT (Design-for-Test) solutions for ASICs and 2.5D SiP (System-in-Package) that supports high test coverage requirements of components and systems.
This role concentrates on Pre-P0 development and works between HW Eng development teams and Supplier Development Teams
Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in diagnostics, and implement in manufacturing tests
Development of innovative DFT IP in collaboration with cross-functional teams inside and outside the company
Work closely with component engineers to resolve high DPPM ASIC issues at EMS partner sites
Engage in test standard working groups, such as IEEE 1149, 1687, P1838, JC-42 Solid State Memories
Trusted advisor on ASIC testability to Juniper teams including ASIC frontend, physical design, DFT, system software, diagnostics, hardware and manufacturing test teams. The influence occurs from the beginning (ASIC kick-off) to production release.
Key advocate recognizing and solving structural vs functional test coverage gaps, as well as weaving in new fault models for advanced semiconductor technology nodes
Demonstrated innovation via patents, published technical papers and conference presentations
Ownership of ASIC test requirements for ASIC MRDs, phase exit validation, advanced test mode development, fault coverage attainment, achievement of manufacturability objectives and continuous improvement
Voice of test authority with ASIC suppliers -- working closely with their product/test teams, quality, design engineering and technologists to correlate and eradicate ASIC failures in our systems with their wafer test, package test and BLCT-1. Able to independently solve NTF (No-Trouble-Found) supplier issues, via creating unique ATE-level tests to solve such issues, per strong knowledge of a chip’s design.
Responsible for influencing supplier testing to implement Juniper-favorable manufacturability modes at their production test
Qualifications
Demonstrated Principal or Distinguished Engineer expertise
A minimum of 15+ years of experience in testability and DFT area for ASICs, memories, and 2.5D SiPs
Excellent knowledge of state-of-the-art DFT techniques in MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and 1687
Strong working level experiences on ASIC DFT implementation, post-silicon validation, debug, and diagnostic integration
Exposure to various semiconductor test challenges and solutions for high-performance ASICs, TSV, HBM (High Bandwidth Memory) DRAM, 2.5D, and 3D ICs
Broad experiences with ASIC suppliers, IP/EDA vendors, 2.5D SiP ecosystems partners, and contract manufacturers
Excellent communication, collaboration and program management skill set. Able to independently influence others.
Education: BS, MS or PhD Electrical Engineering
What We Can Offer You:Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
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Job:
EngineeringJob Level:
TCP_05
"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 153,500 - 291,500 in Massachusetts // 153,500 - 310,500 in California // 135,000 - 310,500 in Texas The listed salary range reflects base salary. Variable incentives may also be offered."Information about employee benefits offered in the US can be found at
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