Principal Engineer – CPU Hardware Telemetry & Silicon Security
- Compensation
- Not disclosed
- Location
- SG
- Work setup
- Remote
- Seniority
- Principal
- Employment
- Not specified
- Experience
- 8+ years
- Category
- Hardware
- Posted
Skills
Must have
- 8+ years of experience in low-level systems programming, CPU performance engineering, kernel development, processor architecture, or related fields.
- Deep understanding of x86-64 CPU microarchitecture, preferably across Intel and AMD processors.
- Strong practical experience working with CPU PMUs, hardware performance counters, or processor profiling systems.
- Advanced proficiency in C/C++ and experience developing performance-sensitive systems software.
- Strong understanding of operating-system internals, kernel/user-mode boundaries, interrupts, scheduling, memory management, and concurrency.
- Practical experience with hardware telemetry, event-based sampling, tracing, or low-level instrumentation.
- Experience diagnosing hardware counter behavior and performance measurement inaccuracies.
- Ability to interpret processor documentation, performance event specifications, and microarchitectural reference manuals.
- Strong debugging, performance optimization, and engineering problem-solving skills.
Nice to have
- Previous engineering experience at Intel, AMD, or a company working extensively with processor performance monitoring.
- Experience developing CPU profiling tools, performance analysis frameworks, or processor observability infrastructure.
- Knowledge of Intel PEBS, Intel PT, LBR, AMD IBS, and vendor-specific performance events.
- Experience with Windows kernel drivers, Linux kernel modules, perf_events, eBPF, or ETW.
- Familiarity with hypervisors, virtual machine execution, and hardware counter virtualization.
- Experience with Rust, assembly language, or low-level instruction-set programming.
- Familiarity with processor power states, CPU topology, SMT, and heterogeneous cores.
- Background in endpoint security, EDR, malware analysis, or behavioral detection.
- Experience integrating real-time telemetry with machine learning systems.
- Contributions to operating-system kernels, profiling tools, processor instrumentation, or related open-source projects.
Full description
About Cyble
Cyble is an AI-native cybersecurity company building the next generation of autonomous cyber defense. Our products combine threat intelligence, endpoint security, exposure management, and AI-powered detection and response to protect enterprises and governments globally.
We are investing in a new frontier of endpoint protection: using processor-level hardware telemetry to detect malicious behavior at the silicon level.
As part of our Cyble Titan EDR initiative, we are building capabilities that leverage modern CPU architectures, hardware performance monitoring, and advanced machine learning to identify ransomware, malware, exploitation, and other sophisticated threats with high accuracy and minimal system overhead.
We are looking for an exceptional engineer to help build the foundation of this technology.
The Role
We are seeking a Principal Engineer specializing in CPU Hardware Telemetry and Low-Level Systems Engineering to design, develop, and optimize telemetry collection capabilities across modern Intel and AMD processors.
You will work at the intersection of CPU microarchitecture, operating systems, security engineering, and machine learning.
Your primary responsibility will be to develop production-grade technologies that reliably extract, normalize, and analyze hardware-level execution signals for real-time threat detection.
This is a deeply technical, hands-on engineering role with the opportunity to influence the architecture of an emerging category of hardware-assisted cybersecurity.
Key Responsibilities
1. CPU Hardware Telemetry Engineering
- Design and implement high-performance telemetry collection using CPU Performance Monitoring Units (PMUs).
- Work with hardware performance counters (HPCs), architectural and model-specific events, and low-level processor instrumentation.
- Develop collection capabilities leveraging:
- Intel Performance Monitoring Counters (PMCs)
- Intel Precise Event-Based Sampling (PEBS)
- Intel Processor Trace (Intel PT)
- Intel Last Branch Records (LBR)
- AMD Instruction-Based Sampling (IBS)
- AMD Performance Monitoring Counters
- Model-Specific Registers (MSRs)
- Identify and characterize hardware events relevant to malware execution, ransomware, privilege escalation, exploitation, and other suspicious behaviors.
- Implement adaptive sampling, counter multiplexing, and efficient collection across CPU generations.